Method of transparently reducing power consumption of a high-speed communication link

A method of reducing power consumption in an integrated circuit communication link having a logic circuitry, the logic circuitry including supply-voltage-critical logic circuitry and non-supply-voltage-critical logic circuitry, the method comprising the steps of:

• synthesizing the integrated circuit to identify the supply-voltage-critical logic circuitry;
• isolating the supply-voltage-critical logic circuitry from the non-supply-voltage-critical logic circuitry, the supply-voltage-critical logic circuitry being driven by a first supply voltage and the non-supply-voltage-critical logic circuitry being driven by a second supply voltage, the first supply voltage being greater than the second supply voltage wherein the first supply voltage is supplied to the communication link and wherein the first supply voltage is used to generate the second supply voltage;
• embedding a voltage regulator in the communication link for supplying the second voltage;
• and
• selectively interfacing the supply-voltage-critical logic circuitry with the non-supply-voltage-critical logic circuitry using level shifters wherein the selectively interfacing step includes the step of selecting a minimal number of points at which the supply-voltage-critical logic circuitry interfaces with the non-supply-voltage-critical logic circuitry.