Techniques for providing calibrated parallel on-chip termination impedance

A method for calibrating a parallel on-chip termination impedance, the method comprising:

• controlling conductive states of first transistors with first calibration codes, the first transistors being coupled in parallel between a first terminal and a supply voltage;
• controlling conductive states of second transistors with second calibration codes, the second transistors being coupled in parallel between the first terminal and a low voltage;
• generating the first calibration codes and the second calibration codes using a feedback loop that receives a signal from the first terminal;
• selecting one of the first calibration codes and one of the second calibration codes to control a parallel on-chip termination impedance of third and fourth transistors at a pin;
• controlling conductive states of fifth transistors with the first calibration codes, the fifth transistors being coupled in parallel between a second terminal and the supply voltage;
• and
• controlling conductive states of sixth transistors with the second calibration codes, the sixth transistors being coupled in parallel between the second terminal and a low voltage.

An integrated circuit comprising a parallel on-chip termination (OCT) calibration circuit, wherein the parallel OCT calibration circuit comprises:

• first transistors coupled in parallel between a first terminal and a supply voltage;
• second transistors coupled in parallel between the first terminal and a low voltage;
• means for comparing a signal from the first terminal with first and second reference signals;
• means for adjusting first calibration codes that control conductive states of the first transistors and second calibration codes that control conductive states of the second transistors until the signal from the first terminal is in a range defined by the first and the second reference signals,
• wherein the means for adjusting selects one of the first calibration codes and one of the second calibration codes to control a parallel on-chip termination impedance of third and fourth transistors at a pin of the integrated circuit;
• fifth transistors coupled in parallel between a second terminal and a supply voltage, wherein the first calibration codes control conductive states of the fifth transistors;
• and
• sixth transistors coupled in parallel between the second terminal and a low voltage, wherein the second calibration codes control conductive states of the sixth transistors.

A parallel on-chip termination (OCT) calibration circuit comprising:

• first transistors coupled in parallel between a first terminal and a supply voltage;
• second transistors coupled in parallel between the first terminal and a low voltage;
• and
• a feedback loop circuit that compares a signal from the first terminal to first and second reference signals to generate first calibration codes that control conductive states of the first transistors and second calibration codes that control conductive states of the second transistors,
• wherein the parallel OCT calibration circuit selects one of the first calibration codes and one of the second calibration codes to control a parallel on-chip termination impedance of third and fourth transistors at a pin, and wherein the selected first calibration code and the selected second calibration code cause at least one of the third transistors and at least one of the fourth transistors to be on at the same time to generate a Thevenin equivalent impedance.