US 7,443,192 B1Granted

Output buffer with digital slew control

AssigneeLattice Semiconductor Corporation

InventorsWilliam B. Andrews, Mou C. Lin, John A. Schadt

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Abstract

An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.

Claims18

Dependent claims

A programmable logic device comprising an output buffer, the output buffer comprising:

a first plurality of output transistors, each having a control terminal and two output terminals, wherein the first plurality of output transistors have paralleled output terminals connected between a first reference node and an output node;
and
a first set of one or more pre-drivers, the first set adapted to generate a plurality of control signals, each control signal coupled to the control terminal of a corresponding output transistor of the first plurality of output transistors, the control signals being generated to sequentially turn on two or more of the first plurality of output transistors, wherein the first set of one or more pre-drivers is adapted to be programmably configured to operate in:
a slew mode in which the control signals are generated to sequentially turn on two or more of the first plurality of output transistors;
and
a non-slew mode in which the control signals are generated to turn on two or more of the first plurality of output transistors substantially simultaneously.

3 more elements

A programmable device comprising an output buffer, the output buffer comprising:

at least two first-polarity output transistors, each output transistor having a control terminal and two output terminals, wherein the output terminals of the at least two first-polarity output transistors are coupled in parallel between a first node and an output node, the first node adapted to couple to a first power source;
and
at least first and second pre-drivers, each pre-driver having at least first and second input nodes and at least first and second output nodes, each first output node coupling to a corresponding one of the control terminals of the two output transistors, the second input node of the second pre-driver being coupled to the second output node of the first pre-driver, and the first input node of the at least first and second pre-drivers being driven by a first input signal;
wherein the first and second pre-drivers are each adapted to be programmably configured to operate in:
a non-slew mode in which an output signal is asserted on the first output node in response to the first input signal being asserted;
and
a slew mode in which, in response to the first input signal on the first input node and an input signal on the second input node being concurrently asserted, an output signal is asserted on the first output node and an output signal is asserted the second output node, the assertion of the output signal on the second output node being delayed with respect to the assertion of the output signal on the first output node.

4 more elements

Dependencies are inferred from the claim text.