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US 7,443,191 B2Granted
Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
AssigneeActel Corporation
InventorWilliam C. Plants
Life of this patent
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Abstract
The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).
Claims11
A method for providing a radiation tolerant programmable logic device, said method comprising:
- providing logic modules;
- providing routing resources coupling said logic modules;
- providing configuration data lines coupled to the memory and having configuration data controlling said logic modules and said routing resources, wherein:
- providing a memory coupled to the configuration data lines for storage of the configuration data, said memory storing the configuration data in error correction code (ECC) word lines in which bits in an ECC word line are separated by at least a double strike distance;
- and
- providing error correction circuitry coupled to said configuration data lines, wherein said error correction circuitry corrects at least single bit errors of ECC word lines read from the memory.
3 more elements
A radiation tolerant programmable logic device comprising:
- logic modules;
- routing resources coupling said logic modules;
- configuration data having configuration data controlling said logic modules and said routing resources, wherein:
- a memory coupled to the configuration data lines for storage of the configuration data, said memory storing the configuration data in error correction code (ECC) word lines in which bits in an ECC word line are separated by at least a double strike distance;
- and
- error correction circuitry coupled to said configuration data lines, wherein said error correction circuitry corrects at least single bit errors of ECC word lines read from the memory.
3 more elements
Dependencies are inferred from the claim text.