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US 7,443,186 B2Granted
On-wafer test structures for differential signals
AssigneeCascade Microtech, Inc.
InventorsEric Strid, Richard Campbell
Life of this patent
Estimating the term…
Abstract
A test structure for characterizing integrated circuits on a wafer includes a differential cell outputting a differential mode signal in response to a differential mode input signal. The probe pads of the test structure are arrayed linearly enabling placement of the test structure in a saw street between dies.
Claims18
A test structure for characterizing a circuit fabricated on a substrate, said test structure comprising:
- (a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to application of a transistor bias voltage to a bias terminal and application of a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to application of said bias voltage to said bias terminal and application of a differential input signal applied to said first signal terminal and said second signal terminal;
- (b) a first probe pad interconnected with said third signal terminal;
- (c) a second probe pad adjacent to said first probe pad and interconnected with said first signal terminal;
- (d) a third probe pad adjacent to said second probe pad and interconnected with said bias terminal;
- (e) a fourth probe pad adjacent to said third probe pad and interconnected to said second signal terminal;
- and
- (f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said fourth signal terminal.
4 more elements
A test structure for characterizing a circuit fabricated on a substrate, said test structure comprising:
- (a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to application of a transistor bias voltage to a bias terminal and application of a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to application of said bias voltage to said bias terminal and application of a differential input signal applied to said first signal terminal and said second signal terminal;
- (b) a first probe pad interconnected to said bias terminal;
- (c) a second probe pad adjacent to said first probe pad and interconnected with said third signal terminal;
- (d) a third probe pad adjacent to said second probe pad and interconnected with said first signal terminal;
- (e) a fourth probe pad adjacent to said third probe pad and interconnected with said bias terminal;
- (f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said second signal terminal;
- (g) a sixth probe pad adjacent to said fifth probe pad and interconnected to said fourth signal terminal;
- (h) a seventh probe pad adjacent to said sixth probe pad and interconnected to said bias terminal.
5 more elements
A test structure for characterizing a circuit fabricated on a substrate, said test structure comprising:
- (a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to application of a transistor bias voltage to a bias terminal and application of a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to application of said bias voltage to said bias terminal and application of a differential input signal applied to said first signal terminal and said second signal terminal;
- (b) a first probe pad interconnected to said bias terminal;
- (c) a second probe pad adjacent to said first probe pad and interconnected with said third signal terminal;
- (d) a third probe pad adjacent to said second probe pad and interconnected with said first signal terminal;
- (e) a fourth probe pad adjacent to said third probe pad and interconnected to said second signal terminal;
- (f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said fourth signal terminal;
- and
- (g) a sixth probe pad proximate said fifth probe pad and interconnected to said bias terminal.
5 more elements
Dependencies are inferred from the claim text.