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US 7,443,150 B2Granted
Switching power supply control with phase shift
AssigneeAnalog Devices, Inc.
InventorTod F. Schiff
Life of this patent
Estimating the term…
Abstract
A control system for a switching power supply shifts the phase of a PWM signal in response to a change in operating conditions. The phase may be shifted by resetting an oscillator that controls the PWM signal. Phase shift logic may include a sample-hold circuit that holds the value of an error signal when the PWM signal switches state. The held error signal may be compared to the real-time error signal, preferably with a user configurable offset. The output of the phase shift logic may be used to reset the oscillator.
Claims6
A switching power supply control system comprising:
- a controller to generate a pulse width modulated (PWM) signal for controlling power to a load through a DC-to-DC switching power supply;
- and
- logic to generate a reset signal to shift the phase of the PWM signal in response to a change in operating conditions;
- where the controller comprises an error amplifier to generate an error signal in response to an output of the power supply;
- and
- where the logic comprises a sample-hold circuit to generate a held error signal by tracking and holding the error signal in response to the PWM signal, and a comparator to generate the reset signal by comparing the error signal to the held error signal.
3 more elements
A switching power supply control system comprising:
- a controller to generate a switching output signal having a period and a duty cycle to control power to a load through a DC-to-DC switching power supply;
- and
- logic to change the period only once in response to an isolated change in operating conditions;
- where the controller comprises:
- an error amplifier to generate an error signal in response to an output of the power supply;
- a clock oscillator to generate a clock signal, the clock oscillator being resettable in response to the reset signal,
- a first comparator having a first input coupled to receive a ramp signal and a second input coupled to receive the error signal;
- and
- a flip-flop to generate the switching output signal, the flip-flop having a first logic input coupled to receive the clock signal and a second logic input coupled to an output of the first comparator;
- and
- where the logic comprises:
- a sample-hold circuit to generate a held error signal by tracking and holding the error signal in response to the PWM signal, and
- a second comparator to generate the reset signal by comparing the error signal to the held error signal.
10 more elements
Dependencies are inferred from the claim text.