Back to results
US 7,443,034 B2Granted
Post passivation interconnection schemes on top of the IC chips
AssigneeMegica Corporation
InventorsMou-Shiung Lin, Jin-Yuan Lee
Life of this patent
Estimating the term…
Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
Claims20
A chip comprising:
- a silicon substrate;
- an ESD circuit in or on said silicon substrate;
- a first internal circuit in or on said silicon substrate;
- a driver, receiver or I/O circuit in or on said silicon substrate;
- a dielectric layer over said silicon substrate;
- a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;
- a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;
- a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;
- a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
- a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure;
- a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure;
- and
- an external connection point connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit.
10 more elements
A chip comprising:
- a silicon substrate;
- an ESD circuit in or on said silicon substrate;
- a first internal circuit in or on said silicon substrate;
- a driver, receiver or I/O circuit in or on said silicon substrate;
- a dielectric layer over said silicon substrate;
- a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;
- a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;
- a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride, and wherein one of multiple openings in said passivation layer has a transverse dimension between 0.5 and 30 micrometers;
- a first via in one of said multiple openings, wherein said first via is connected to said first interconnecting structure;
- a second via in one of said multiple openings, wherein said second via is connected to said second interconnecting structure;
- a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure;
- and
- an external connection point connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit.
10 more elements
A chip comprising:
- a silicon substrate;
- an ESD circuit in or on said silicon substrate;
- a first internal circuit in or on said silicon substrate;
- a driver, receiver or I/O circuit in or on said silicon substrate;
- a dielectric system over said silicon substrate;
- a first interconnecting structure over said silicon substrate and in said dielectric system, wherein said first interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit;
- a second interconnecting structure over said silicon substrate and in said dielectric system, wherein said second interconnecting structure is connected to said first internal circuit;
- multiple metal layers in said dielectric system, wherein said dielectric system comprises multiple dielectric layers between said multiple metal layers;
- a passivation layer over said dielectric system and over said multiple metal layers, wherein said passivation layer comprises a nitride;
- a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
- a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure;
- a third interconnecting structure over said passivation layer and over said first and second vias, wherein said third interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer and greater than those of said multiple metal layers, and wherein said first terminal is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure;
- and
- an external connection point connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit.
11 more elements
Dependencies are inferred from the claim text.