US 7,442,998 B2Granted

Non-volatile memory device

AssigneePowerchip Semiconductor Corp.

InventorsHoung-Chi Wei, Saysamone Pittikoun, Wei-Chung Tseng

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Abstract

A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a plurality of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.

Claims8

Dependent claims

A non-volatile memory, comprising:

a substrate;
a plurality of first memory units disposed on the substrate, wherein the first memory units are separated from one another by a gap and each first memory unit comprises a first composite layer, a first gate and a cap layer sequentially formed over the substrate;
a plurality of second memory units disposed in the gaps between the first memory units, wherein each second memory unit comprises a second composite layer and a second gate sequentially formed over the substrate and the second memory units together with the first memory units form a memory cell column;
a plurality of insulating spacers disposed between the first memory units and the second memory units;
a source region and a drain region disposed in the substrate on the respective sides of the memory cell column;
a first inter-layer insulating layer disposed on the substrate;
a source line disposed in the first inter-layer insulating layer for connecting with the source region;
a plurality of metallic lines disposed in the first inter-layer insulating layer aligned in a direction perpendicular to the memory cell column for connecting with the second gate of the second memory cell units;
a second inter-layer insulating layer disposed on the first inter-layer insulating layer;
and
a bit line disposed on the second inter-layer insulating layer for connecting electrically with the drain region through a conductive plug.

8 more elements

A non-volatile memory, comprising:

a substrate;
a plurality of first memory units disposed on the substrate, wherein the first memory units are separated from one another by a gap and each first memory unit comprises a first composite layer, a first gate and a cap layer sequentially formed over the substrate;
a plurality of second memory units disposed in the gaps between the first memory units, wherein each second memory unit comprises a second composite layer and a second gate sequentially formed over the substrate and the second memory units together with the first memory units form a memory cell column;
a plurality of insulating spacers disposed between the first memory units and the second memory units;
a source region and a drain region disposed in the substrate on the respective sides of the memory cell column;
a first inter-layer insulating layer disposed on the substrate;
a source line disposed in the first inter-layer insulating layer for connecting with the source region;
a second inter-layer insulating layer disposed on the first inter-layer insulating layer;
a third inter-layer insulating layer disposed on the second inter-layer insulating layer;
a first conductive line disposed in the third inter-layer insulating layer for connecting with the source line through a first conductive plug in the second inter-layer insulating layer;
a plurality of second conductive lines disposed in the third inter-layer insulating layer for connecting with the second gates through a plurality of second conductive plugs in the first inter-layer insulating layer and the second inter-layer insulating layer;
and
a bit line disposed on the third inter-layer insulating layer for connecting electrically with the drain region trough a third conductive plug.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/162,648Filed 18 Sep 2005
Priority: TW 94107083 A9 Mar 2005
Published: US 2006/0234446 A119 Oct 2006
Granted: 28 Oct 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors
H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors