Structure and method for enhanced triple well latchup robustness

A complementary metal oxide semiconductor device comprising:

• a substrate with a first conductivity type;
• a first semiconductor layer with said first conductivity type above said substrate, wherein first semiconductor layer is doped with a higher concentration of a first conductivity type dopant relative to said substrate;
• a second semiconductor layer with a second conductivity type different from said first conductivity type between said substrate and said first semiconductor layer, wherein said first semiconductor layer and said second semiconductor layer each have defined outer edges and wherein said second semiconductor layer is longer than said first semiconductor layer and extends laterally beyond said defined outer edges of said first semiconductor layer;
• and
• a first semiconductor well with said second conductivity type above said second semiconductor layer and not above said first semiconductor layer such that vertical bipolar cuffent gain is degraded;
• and
• a second semiconductor well with said first conductivity type adjacent to said first semiconductor well and above both said first semiconductor layer and said second semiconductor layer so as to both compensate for threshold voltage scattering and isolate said second semiconductor well from said substrate, wherein said second semiconductor well and said first semiconductor layer are aligned and have approximately equal lengths.