US 7,442,989 B2 · Nonvolatile semiconductor memory device and method of manufacturing thereof

Abstract

This invention is intended to improve reliability of a nonvolatile semiconductor memory device and reduces a memory cell size of the nonvolatile semiconductor memory device. A memory cell which includes source/drain diffusion layers in a p-type well formed in a silicon substrate, silicon nitride dots which are located between silicon oxide films and into which charges are injected, a control gate 212, and assist gates is formed. Programming is conducted to the memory cell by injecting electrons into the drain-side silicon nitride dots or the source-side silicon nitride dots. Since silicon nitride serving as a charge injected section is in the form of dots, it is possible to suppress movement of the charges in a channel direction, to prevent the charges on a source end portion and those on a drain end portion from being mixed together, and to improve charge holding characteristic of the memory cell. Even in the case where a gate length is shortened, the charge holding characteristic can be secured.

Claims20

Dependent claims

A nonvolatile semiconductor memory device comprising:

(a) a first insulator film formed above a semiconductor substrate;
(b) silicon nitride dots formed on said first insulator film;
(c) a second insulator film formed on said silicon nitride dots;
(d) a conductive film formed on said second insulator film;
(e) first and second semiconductor regions formed in said semiconductor substrate;
(f) a channel region located between said first and second semiconductor regions, wherein
(g) programming is performed by injecting charges from said channel region into said silicon nitride dots on a first end portion of said channel region on a side of said first semiconductor region or into said silicon nitride dots on a second end portion of said channel region on a side of said second semiconductor region, and wherein
(h) said and second insulator films are silicon oxide films, and wherein
(i) surface portions of said silicon nitride dots are higher in nitrogen concentration than central portions of said silicon nitride dots.

6 more elements

A nonvolatile semiconductor memory device comprising:

(a) first and second semiconductor regions formed in a semiconductor substrate;
(b) a channel region located between said first and second semiconductor regions;
(c) a first insulator film formed above said semiconductor substrate, and extending from above said channel region toward above said first semiconductor region;
(d) a first conductive film formed on said first insulator film;
(e) a second insulator film formed above said semiconductor substrate, and extending from above said channel region toward above said second semiconductor region;
(f) a second conductive film formed on said second insulator film;
(g) a third insulator film formed above said semiconductor substrate between said first and second conductive films;
(h) silicon nitride dots formed on said third insulator film;
(i) a fourth insulator film formed on said silicon nitride dots;
and
(j) a third conductive film formed on said silicon nitride dots, wherein
(k) programming is performed by injecting charges from said channel region into said silicon nitride dots on a first end portion on a side of said first conductive film or into said silicon nitride dots on a second end portion on a side of said second conductive film, and wherein
(l) said third and fourth insulator films are silicon oxide films, and wherein
(m) surface portions of said silicon nitride dots are higher in nitrogen concentration than central portions of said silicon nitride dots.

11 more elements

A nonvolatile semiconductor memory device comprising:

(a) first and second semiconductor regions formed in a semiconductor substrate;
(b) a channel region located between said first and second semiconductor regions;
(c) a first insulator film formed above said semiconductor substrate, and extending from above said channel region toward above said first semiconductor region;
(d) a first conductive film formed on said first insulator film;
(e) a second insulator film formed above said semiconductor substrate, and extending from above said channel region toward above said second semiconductor region;
(f) a second conductive film formed on said second insulator film;
(g) a third insulator film formed above said semiconductor substrate between said first and second conductive films;
(h) silicon nitride dots formed on said third insulator film;
(i) a fourth insulator film formed on said silicon nitride dots;
and
(j) a third conductive film formed on said fourth insulator film,
wherein programming is performed by injecting charges from said channel region into said silicon nitride dots on a first end portion on a side of said first conductive film or into said silicon nitride dots on a second end portion on a side of said second conductive film,
said third and fourth insulator films are silicon oxide films,
injection of said charges into said silicon nitride dots on said first end portion is conducted by carrying electrons from said first semiconductor region toward said second semiconductor region,
injection of said charges into said silicon nitride dots on said second end portion is conducted by carrying electrons from said second semiconductor region toward said first semiconductor region,
said charges injected into said silicon nitride dots on said first end portion are determined by carrying the electrons from said second semiconductor region to said first semiconductor region,
said charges injected into said silicon nitride dots on said second end portion are determined by carrying the electrons from said first semiconductor region to said second semiconductor region, and
surface portions of said silicon nitride dots are higher in nitrogen concentration than central portions of said silicon nitride dots.

15 more elements

Dependencies are inferred from the claim text.

Nonvolatile semiconductor memory device and method of manufacturing thereof

Life of this patent

Nonvolatile semiconductor memory device and method of manufacturing thereof

Life of this patent

Abstract

Claims20