Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same

A nonvolatile semiconductor memory device, comprising:

• over a main surface of a semiconductor substrate,
• a first insulator and a first gate electrode formed on said first insulator;
• a second insulator formed on a sidewall of said first gate electrode and on the main surface of said semiconductor substrate on one or both sides of said first gate electrode;
• a third insulator formed on said second insulator;
• a fourth insulator formed on said third insulator;
• a second gate electrode formed in a self-aligned manner on the sidewall of said first gate electrode and at a position opposite to the main surface of said semiconductor substrate on both sides of said first gate electrode via said second to fourth insulators;
• and
• a fifth insulator formed in a self-aligned manner on a side surface of said second gate electrode opposite to a side on which said fourth insulator is formed,
• wherein said second gate electrode has a discontinuity of an inclined angle on a side surface of said fifth insulator, and
• wherein a recess amount of said first gate electrode to an uppermost edge of said first gate electrode is from one-third of the gate length of said second gate electrode to the gate length thereof.

A nonvolatile semiconductor memory device, comprising:

• over a main surface of a semiconductor substrate,
• a first insulator and a first gate electrode formed on said first insulator;
• a spacer formed on a sidewall of said first gate electrode and at a position being in contact with a surface of said semiconductor substrate on one or both sides of said first gate electrode;
• a second insulator formed on said spacer;
• a third insulator formed on the surface of said semiconductor substrate on both sides of said first gate electrode;
• a fourth insulator formed on said second and third insulators;
• a fifth insulator formed on said fourth insulator;
• and
• a second gate electrode made of a conductive material formed on a sidewall of said first gate electrode and at a position opposite to the main surface of said semiconductor substrate on one or both sides of said first gate electrode via said spacer and said second to fifth insulators,
• wherein said spacer has a round shape at a lowermost portion of a side surface thereof being out of contact with said first gate electrode, and
• a thickness of said fifth insulator at said corner portion of said fifth insulator is 80% or more of that of said fifth insulator on a flat portion.