Semiconductor device n-channel type MOS transistor with gate electrode layer featuring small average polycrystalline silicon grain size
AssigneeNEC Electronics Corporation
InventorsMitsuhiro Togo, Takayuki Suzuki
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Abstract
In a semiconductor device including a semiconductor substrate, and an n-channel type MOS transistor produced in the semiconductor substrate, the n-channel type MOS transistor includes a gate insulating layer formed on the semiconductor substrate and having a thickness of at most 1.6 nm, and a gate electrode layer on the gate insulating layer, and the gate electrode layer is composed of polycrystalline silicon which has an average grain size falling within a range between 10 nm and 150 nm in the vicinity of the gate insulating layer.
Claims5
A method for manufacturing a semiconductor device, which comprises:
- preparing a semiconductor substrate;
- forming an insulating layer on said semiconductor device, said insulating layer having a thickness of at most 1.6 nm;
- forming a polycrystalline silicon layer on said insulating layer;
- implanting n-type impurities into said polycrystalline silicon layer;
- implanting inert gas molecules or atoms into said polycrystalline silicon layer;
- forming a gate electrode structure including a gate insulating layer derived from said insulating layer, and a gate electrode layer derived from said polycrystalline silicon layer;
- and
- subjecting said gate electrode structure to an annealing process so that the polycrystalline silicon in said gate electrode layer has an average grain size falling within a range between 10 nm and 150 nm.
A method for manufacturing a semiconductor device, which comprises:
- preparing a semiconductor substrate;
- forming a first insulating layer on said semiconductor device, said insulating layer having a thickness of at most 1.6 nm;
- forming a first polycrystalline silicon layer on said insulating layer;
- forming a second insulating layer on said first polycrystalline silicon layer;
- forming a second polycrystalline silicon layer on said second insulating layer;
- implanting n-type impurities into said first and second polycrystalline silicon layers;
- implanting inert gas molecules or atoms into said first and second polycrystalline silicon layers;
- forming a gate electrode structure including a gate insulating layer derived from said first insulating layer, a first gate electrode layer derived from said first polycrystalline silicon layer, a stopper layer derived from said second insulating layer, and a second gate electrode layer derived from said second polycrystalline silicon layer;
- and
- subjecting said gate electrode structure to an annealing process so that the polycrystalline silicon in said first gate electrode layer has an average grain size falling within a range between 10 nm and 150 nm.
Dependencies are inferred from the claim text.