US 7,442,621 B2 · Semiconductor process for forming stress absorbent shallow trench isolation structures

Abstract

A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

Claims15

Dependent claims

A semiconductor fabrication process, comprising:

patterning a photoresist layer over a semiconductor substrate to expose an isolation region of the substrate, wherein the substrate is a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer overlying a substrate bulk and an active semiconductor active layer overlying the BOX layer;
forming a trench in the isolation region;
forming a first dielectric in the trench to partially fill the trench wherein the first dielectric is a flowable dielectric;
depositing a capping dielectric overlying the first dielectric to create a trench isolation structure;
forming a material adjacent a first sidewall of the trench to create stress in the substrate adjacent the first sidewall, wherein the trench isolation structure prevents the stress adjacent the first sidewall from causing stress adjacent a second sidewall of the trench;
and
prior to patterning the photoresist layer, forming a hard mask layer overlying the substrate, wherein the hard mask comprises silicon nitride.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor process for forming stress absorbent shallow trench isolation structures

Life of this patent

Semiconductor process for forming stress absorbent shallow trench isolation structures

Life of this patent

Abstract

Claims15