Method of manufacturing a transistor and a method of forming a memory device with isolation trenches

A method of manufacturing a transistor in a semiconductor substrate, comprising:

• defining isolation trenches in a surface of a semiconductor substrate, for laterally confining an active area in which the transistor is to be formed, one active area being laterally confined by two isolation trenches;
• filling the isolation trenches with an isolating material;
• providing a gate electrode which is insulated from the active area by a gate insulating material;
• providing a first and a second source/drain regions, wherein a conductive channel is formed between the first and second source/drain regions;
• wherein providing the gate electrode comprises:
• defining a gate groove in the substrate and in each of the isolation trenches at a portion adjacent to the active area so that finally a gate groove extends in the active area and in an adjacent portion of each of the insulator trenches from the surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate to a first depth;
• defining a plate-like portion in each of the isolation trenches at a position adjacent to the gate groove so that the two plate-like portions are connected with the gate groove and the gate groove is disposed between the two plate-like portions, the two plate-like portions extending to a second depth larger than the first depth;
• providing a gate insulating material at an interface between the active area and the gate groove and at an interface between the active area and the plate-like portions;
• and
• depositing a gate electrode material so as to fill the gate groove and the two plate-like portions.

A method of manufacturing a memory device, comprising:

• providing a plurality of storage capacitors for storing information;
• defining isolation trenches in a surface of a semiconductor substrate, for laterally confining active areas in which access transistors are to be formed, one active area being laterally confined by two isolation trenches;
• filling the isolation trenches with an isolating material;
• providing a plurality of array gate electrodes of the access transistors, each of the array gate electrodes being insulated from the active area by a gate insulating material;
• providing a plurality of first and second source/drain regions of the access transistors, a conductive channel being formed between each of the first and a corresponding one of the second source/drain regions, each of the first source/drain regions being connected with a storage electrode of a corresponding one of the storage elements;
• providing bitlines extending in a first direction along the substrate, the bitlines being connected with the second source/drain regions of the access transistors via bitline contacts;
• providing word lines extending in a second direction along the substrate, the second direction intersecting the first direction, the gate electrode of the access transistors being connected with one of the word lines;
• and
• providing peripheral circuitry by providing at least one peripheral transistor, the process of providing a peripheral transistor comprising:
• providing a first and a second peripheral source/drain regions, a peripheral channel connecting the first and the second peripheral source/drain regions;
• providing a peripheral gate insulating layer and providing a peripheral gate electrode controlling the conductivity of the peripheral channel, wherein the peripheral gate electrodes and the word lines are made by forming a layer stack comprising at least one layer on the substrate surface so as to cover the memory cells and the peripheral circuitry and, subsequently patterning the layer stack so as to form the word lines and the peripheral gate electrodes, wherein the process of providing a gate electrode comprises:
• defining a gate groove in the substrate and in each of the isolation trenches at a portion adjacent to the active area so that finally a gate groove extends in the active area and in an adjacent portion of each of the isolation trenches from the surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate to a first depth;
• defining a plate-like portion in each of the isolation trenches at a position adjacent to the gate groove so that the two plate-like portions are connected with the gate groove and the gate groove is disposed between the two plate-like portions, the two plate-like portions extending to a second depth larger than the first depth, wherein the process of defining a plate-like portion is an etching process which etches the isolating material of the isolation trenches selectively with respect to the substrate material;
• providing a gate insulating material at an interface between the active area and the gate groove and at an interface between the active area and the plate-like portions;
• and
• depositing a gate electrode material so as to fill the gate groove and the two plate-like portions.