Stress enhanced CMOS circuits and methods for their fabrication

A method for fabricating a stress enhanced CMOS circuit comprising the steps of:

• forming a PMOS transistor;
• forming a first NMOS transistor adjacent the PMOS transistor in a channel width direction and a second NMOS transistor adjacent the PMOS transistor in a channel length direction, the PMOS transistor separated from the first NMOS transistor and the second NMOS transistor by an isolation region therebetween;
• forming a dummy region overlying the isolation region between the PMOS transistor and the second NMOS transistor;
• depositing a compressive stress liner;
• etching the compressive stress liner to remove the compressive stress liner from the first NMOS transistor, the second NMOS transistor, a portion of the isolation region between the PMOS transistor and the first NMOS transistor, and from a portion of the dummy region;
• depositing a tensile stress liner overlying the compressive stress liner;
• and
• etching the tensile stress liner to remove the tensile stress liner from a portion of the compressive stress liner and a portion of the dummy region.

A method of fabricating a stress enhanced CMOS circuit comprising a first NMOS transistor and a PMOS transistor separated by an isolation region and a second NMOS transistor spaced apart from the PMOS transistor, the method comprising the steps of:

• forming a dummy region between the second NMOS transistor and the PMOS transistor;
• depositing a compressive stress liner overlying the PMOS transistor but not the first NMOS transistor;
• etching the compressive stress liner and leaving a remaining portion of the compressive stress liner overlying a first portion of the dummy region;
• depositing a tensile stress liner overlying the first NMOS transistor and a portion but not the entirety of the compressive stress liner and a portion but not the entirety of the PMOS transistor;
• and
• etching the tensile stress liner and leaving a remaining portion of the tensile stress liner overlying a second portion of the dummy region and spaced apart from the remaining portion of the compressive stress liner.

A method for fabricating a stress enhanced CMOS circuit comprising the steps of:

• forming a first NMOS transistor and forming a second NMOS transistor;
• forming a PMOS transistor adjacent the first NMOS transistor in a channel width direction and adjacent the second NMOS transistor in a channel length direction, the PMOS transistor and the first NMOS transistor separated by an isolation region therebetween;
• depositing and patterning a dummy region positioned between the second NMOS transistor and the PMOS transistor;
• depositing a compressive stress liner overlying the first NMOS transistor, the PMOS transistor, and the isolation region;
• etching the compressive stress liner to remove the compressive stress liner from the first NMOS transistor and from a portion of the isolation region;
• depositing a tensile stress liner overlying the first NMOS transistor, the PMOS transistor, and the isolation region;
• and
• etching the tensile stress liner to remove a portion of the tensile stress liner overlying the compressive stress liner and leaving the tensile stress liner overlying the first NMOS transistor, the isolation region, and a portion of the compressive stress liner.

A method of fabricating a stress enhanced CMOS circuit comprising a first NMOS transistor and a PMOS transistor separated by an isolation region and a second NMOS transistor spaced apart from the PMOS transistor, the method comprising the steps of:

• forming a dummy region between the second NMOS transistor and the PMOS transistor;
• providing a compressive stress liner overlying the PMOS transistor but not the first NMOS transistor by depositing and etching the compressive stress liner and leaving a remaining portion of the compressive stress liner overlying a first portion of the dummy region;
• and
• providing a tensile stress liner overlying the first NMOS transistor and a portion but not the entirety of the compressive stress liner by depositing and etching the tensile stress liner and leaving a remaining portion of the tensile stress liner overlying a second portion of the dummy region and spaced apart from the remaining portion of the compressive stress liner.