US 7,442,600 B2Granted

Methods of forming threshold voltage implant regions

AssigneeMicron Technology, Inc.

InventorsHongmei Wang, Kurt D. Beigel, Fred D. Fishburn, Rongsheng Yang

Life of this patent

Estimating the term…

Loading patent…

Abstract

The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

Claims11

Dependent claims

A method of forming threshold voltage implant regions, comprising:

providing a semiconductor substrate, the substrate having at least two channel region locations defined therein, one of the at least two channel region locations being a first channel region location and another of the at least two channel region locations being a second channel region location, the first and second channel region locations having first and second areas, respectively;
using a mask to block a portion of the first area, and to block a portion of the second area;
the percentage of the second area blocked with the mask being larger than the percentage of the first area blocked with the mask;
the mask blocking only portions of the first and second areas to leave unblocked portions of the first and second channel region locations;
while the mask blocks the portions of the first and second areas, conducting an implant of threshold voltage dopant into the unblocked portions of the first and second channel region locations to form threshold voltage implant regions within the first and second channel region locations;
and
diffusing the dopant throughout portions of the first and second channel region locations blocked by the mask during the implant so that concentrations of the threshold voltage dopant in the unblocked portions of the first and second channel region locations are substantially similar to concentrations of the threshold voltage dopant in the blocked portions of the first and second channel region locations.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/925,736Filed 24 Aug 2004
Published: US 2006/0046381 A12 Mar 2006
Granted: 28 Oct 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10P 30/21
Into semiconductor materials, e.g. for doping: of electrically active species
H10D 30/0217
Of FETs having insulated gates [IGFET]: forming self-aligned punch-through stoppers or threshold implants under gate regions
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 84/0128
The components including insulated gates, e.g. IGFETs: manufacturing their channels