Flexible memory built-in-self-test (MBIST) method and apparatus
OwnerNilanjan Mukherjee, Xiaogang Du +1inventors
InventorsNilanjan Mukherjee, Xiaogang Du, Wu-Tung Cheng
Life of this patent
Estimating the term…
Abstract
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
Claims27
An integrated circuit comprising at least one memory comprising an array of cells, each cell having a row address and a column address, the integrated circuit further comprising at least one memory built in self test (MBIST) circuit coupled to the at least one memory, the MBIST circuit comprising:
- a decoder adapted to decode programming instructions, the programming instructions comprising configuration instruction words and algorithm instruction words, the decoder being adapted to distinguish algorithm instruction words from configuration instruction words and to separately decode the algorithm instruction words and the configuration instructions words, the configuration instruction words comprising an algorithm designating portion designating at least one test algorithm, the test algorithm comprising test steps to be applied to test the memory in accordance with the test algorithm, the algorithm instruction words comprising memory access operation portions that designate memory operations to be performed during test steps.
An integrated circuit comprising at least one memory to be tested and a memory built in test (MBIST) circuit, the MBIST circuit being configured to apply at least one testing algorithm to the at least one memory in response to the instructions received from automated test equipment (ATE), the MBIST circuit comprising:
- instruction memory adapted to receive instructions from the ATE;
- an instruction decoder operable to decode said instructions and to separate configuration instructions from algorithm instructions;
- an address generator responsive to the decoded instructions for addressing cells of the memory being tested in accordance with an addressing scheme determined from the decoded instructions, the addressing scheme addressing cells of the memory such that the application of test data to the addressed cells results in the execution of said at least one test algorithm to test the at least one memory;
- a data generator for applying test data to addressed memory cells to perform said at least one test algorithm on the memory as determined from the decoded instructions, the memory producing test response outputs from at least selected cells receiving data from the data generator;
- an output response analyzer operable to compare expected response data with the actual test response output from the selected cell so as to provide test results;
- and
- the integrated circuit also comprising a diagnostic monitor for recording diagnostic data when a fault is indicated by the test results.
An apparatus comprising:
- means for receiving configuration instruction words and algorithm instruction words;
- means for decoding configuration instruction words and algorithm instruction words;
- means responsive to the decoded programming instructions for addressing cells of the memory to accomplish the execution of at least one testing algorithm on the memory cells;
- means for applying data to the addressed cells in accordance with the decoded programming instructions and for providing an output of expected responses from address cells to the applied data;
- means for analyzing at least selected expected responses from cells of the memory with test data outputs from address cells in response to applied data to provide test results for the memory;
- and
- means for collecting diagnosing data from the test results.
Dependencies are inferred from the claim text.