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US 7,434,073 B2Granted
Frequency and voltage scaling architecture
AssigneeIntel Corporation
InventorsGrigorios Magklis, José González, Antonio González
Life of this patent
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Abstract
A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.
Claims27
A processor comprising:
- a first clock domain having a first clock signal frequency and a first operating voltage, the first clock domain including an instruction decoder and a branch prediction unit;
- a second clock domain having a second clock signal frequency and a second operating voltage, the second clock domain including execution units;
- and
- a third clock domain having a third clock signal frequency and a third operating voltage, the third clock domain including a second level cache memory, wherein the first and second clock domains' clock signal frequency and operating voltage are controlled according to a ratio of energy-delay2 products, wherein the numerator of the ratio is the energy-delay2 product for a first time interval and the denominator of the ratio is the energy-delay product for a second time interval, the second time interval being prior to the first time interval.
1 more element
A method comprising:
- determining energy and delay of a processor clock domain for a first interval of time;
- determining energy and delay of the processor clock domain for a second interval of time, wherein the second interval of time is later than the first interval of time;
- adjusting an operating voltage and a clock signal frequency of the processor clock domain such that a ratio of a product of the energy and delay for the second time interval and a product of the energy and delay for the first time interval is minimized.
A system comprising:
- a memory to store a plurality of instructions;
- a processor including a plurality of clock domains having a plurality of independent clock frequencies and independent operating voltages dependent upon a number of the plurality of instructions to be executed by the processor, wherein the plurality of independent clock frequencies and independent operating voltages are to be adjusted such that a ratio of an energy-delay2 product corresponding to a first interval of time and an energy-delay2 product corresponding to a second interval of time is minimized for each of the plurality of clock domains.
A machine-readable medium having stored thereon a set of instructions, which when executed by a machine, cause the machine to perform a method comprising:
- determining energy and delay of a processor clock domain for a first interval of time;
- determining energy and delay of the processor clock domain for a second interval of time, wherein the second interval of time is later than the first interval of time;
- adjusting an operating voltage and a clock signal frequency of the processor clock domain such that a product of the energy and delay for the second interval of time is minimized.
Dependencies are inferred from the claim text.