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US 7,433,231 B2Granted
Multiple select gates with non-volatile memory cells
AssigneeMicron Technology, Inc.
InventorSeiichi Aritome
Life of this patent
Estimating the term…
Abstract
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.
Claims21
A memory array, comprising:
- a number of non-volatile memory cells;
- a number of select gates coupled in series to the number of non-volatile memory cells;
- wherein a first select gate includes a control gate and a floating gate electrically connected together by a conductive strap through a dielectric layer;
- and
- wherein a second select gate includes a control gate and a floating gate which are electrically coupled but separated by a dielectric layer.
2 more elements
A memory array, comprising:
- a NAND string of non-volatile memory cells;
- a number of source select gates on a source side of the string;
- a drain select gate on a drain side of the string;
- and
- wherein the number of source select gates includes at least one source select gate having a control gate and a floating gate electrically connected together by a conductive strap through a dielectric layer, and includes at least one source select gate having a control gate and a floating gate which are electrically separated by a dielectric layer.
2 more elements
A memory array, comprising:
- a string of non-volatile memory cells;
- a number of source select gates on a source side of the string and coupled in series with the string;
- a number of drain select gates on a drain side of the string and coupled in series with the string;
- and
- wherein at least one select gate on a cell side of the string has a control gate and a floating gate electrically separated by a dielectric layer from one another and is coupled in series with at least one select gate having a control gate and a floating gate which are electrically connected by a conductive strap through a dielectric layer.
2 more elements
A memory device, comprising:
- an array of non-volatile memory cells including a string of non-volatile memory cells;
- circuitry for control and access to the array of non-volatile memory cells;
- wherein the array of non-volatile memory cells includes:
- a first number of select gates coupled to a source side of the string of non-volatile memory cells, wherein a first one of the first number of select gates is coupled to a source line and has a control gate and a floating gate electrically connected together by a conductive strap through a dielectric layer, and wherein a second one of the first number of select gates is coupled to a first one of the string of non-volatile memory cells and has a control gate and a floating gate electrically separated by a dielectric layer from one another;
- and
- a second number of select gates coupled to a drain side of the string of non-volatile memory cells, and wherein a last one of the second number of select gates is coupled to a bit line.
3 more elements
A memory module, comprising:
- a number of contacts;
- two or more memory devices, each having access lines selectively coupled to the number of contacts;
- and
- wherein at least one of the memory devices includes:
- an array of non-volatile memory cells including a string of non-volatile memory cells;
- circuitry for control and access to the array of non-volatile memory cells;
- wherein the array of non-volatile memory cells includes:
- a pair of source select gates series coupled to the string, wherein a first one of the source select gates has a control gate and a floating gate electrically connected together by a conductive strap through a dielectric layer, and wherein a second one of the source select gates has a control gate and a floating gate which are separated by a dielectric;
- and
- a pair of drain select gates series coupled to the string.
7 more elements
An electronic system, comprising:
- a processor, and
- a memory device coupled to the processor, wherein the memory device includes:
- an array of non-volatile memory cells including a NAND string;
- circuitry for control and access to the array of non-volatile memory cells;
- and
- wherein the ray of non-volatile memory cells includes:
- a first and a second source select gate series connected to the NAND string, wherein:
- the first source select gate has a control gate and a floating gate which are electrically connected by a conductive strap through a dielectric layer;
- and
- the second source select gate has a control gate and a floating gate separated by a dielectric, and has a threshold voltage and a cell size which are substantially equal to a threshold voltage and a cell size of each non-volatile memory cell in the NAND string;
- and
- a drain select gate connected to the NAND string, the drain select gate has a control gate and a floating gate which are electrically connected by a conductive strap through a dielectric layer.
9 more elements
Dependencies are inferred from the claim text.