# US 7,423,903 B2 · Single-gate non-volatile memory and operation method thereof

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- Number: US 7,423,903 B2
- Document ID: US7423903B2
- Status: Granted
- Kind: B2
- Application number: 11/403,858
- Filed: 2006-04-14
- Published: 2007-10-18
- Granted: 2008-09-09
- Earliest claimed: 2006-04-14
- Assignees: Yield Microelectronics Corp.
- Inventors: Hsin-Chang Lin; Wen-Chien Huang; Ming-Tsang Yang; Hao-Cheng Chang; Cheng-Ying Wu
- Web page: https://patentgrep.com/patent/US7423903B2

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

## Claims

### Claim 1

An operation method of a single-gate non-volatile memory,
wherein said single-gate non-volatile memory comprises:
a P-type semiconductor substrate;
a transistor, disposed in said P-type semiconductor substrate, and having a first electrically-conductive gate and a plurality of first ion-doped regions, said first ion-doped regions separately disposed at both sides of said first electrically-conductive gate and respectively functioning as the source and the drain; and
a capacitor structure, disposed in said P-type semiconductor substrate, and having a second electrically-conductive gate and a second ion-doped region; wherein said first electrically-conductive gate and said second electrically-conductive gate being electrically interconnected to form a single floating gate; wherein said operation method is characterized in:
a substrate voltage Vsub, a source voltage Vs, a drain voltage Vd, a control gate voltage Vc are respectively applied to said P-type semiconductor substrate, said source, said drain and said second ion-doped region, and said voltages meet the following conditions:
in writing said memory:
Vsub is grounded, and
Vd>Vs>0, and
Vc>Vs>0; and
in erasing said memory:
Vsub is grounded, and
Vd>Vc>Vs≧0.

### Claim 2

An operation method of a single-gate non-volatile memory,
wherein said single-gate non-volatile memory comprises:
a P-type semiconductor substrate;
a transistor, disposed in said P-type semiconductor substrate, and having a first electrically-conductive gate and a plurality of first ion-doped regions, said first ion-doped regions separately disposed at both sides of said first electrically-conductive gate and respectively functioning as the source and the drain;
an N-type well, disposed below said first ion-doped regions; and
a capacitor structure, disposed in said P-type semiconductor substrate, and having a second electrically-conductive gate and a second ion-doped region; wherein said first electrically-conductive gate and said second electrically-conductive gate being electrically interconnected to form a single floating gate; wherein said operation method is characterized in:
a substrate voltage Vsub, an N-type well voltage Vnwell, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc are respectively applied to said P-type semiconductor substrate, said N-type well, said source, said drain and said second ion-doped region, and said voltages meet the following conditions:
in writing said memory:
Vsub is grounded, and
Vnwell≧Vs>Vd>0, and
Vc>Vd>0; and
in erasing said memory:
Vsub is grounded, and
Vc>0, and
Vnwell≧Vs>Vd≧0.

### Claim 3

An operation method of a single-gate non-volatile memory,
wherein said single-gate non-volatile memory comprises:
an N-type semiconductor substrate;
a P-type well, disposed in said N-type semiconductor substrate;
a transistor, disposed on the surface of said P-type well, and having a first electrically-conductive gate and a plurality of first ion-doped regions, said first ion-doped regions separately disposed at both sides of said first electrically-conductive gate and respectively functioning as the source and the drain; and
a capacitor structure, disposed on the surface of said P-type well, and having a second electrically-conductive gate and a second ion-doped region; wherein said first electrically-conductive gate and said second electrically-conductive gate being electrically interconnected to form a single floating gate; wherein said operation method is characterized in:
a substrate voltage Vsub, a P-type well voltage Vpwell, a source voltage Vs, a drain voltage Vd, and a control gate voltage Vc, are respectively applied to said N-type semiconductor substrate, said P-type well, said source, said drain and said second ion-doped region, and said voltages meet the following conditions:
in writing said memory:
Vsub is connected to a power supply, and
Vd>Vs>Vpwell, and
Vc>Vs>Vpwell; and
in erasing said memory:
Vsub is connected to a power supply, and
Vd>Vs≧Vpwell, and
Vd>Vs≧Vpwell.

### Claim 4 (depends on 3)

The operation method of a memory of claim 3, wherein said P-type well voltage Vpwell meet, Vpwell24 0 in writing said memory.

### Claim 5 (depends on 3)

The operation method of a memory of claim 3, wherein said P-type well voltage Vpwell meet, Vpwell≧0 in erasing said memory.

### Claim 6 (depends on 5)

The operation method of a memory of claim 5, wherein said source voltage Vs, said drain voltage Vd and said control gate voltage Vc, meet, Vd>Vc>Vs≧0 in erasing said memory.

### Claim 7

An operation method of a single-gate non-volatile memory,
wherein said single-gate non-volatile memory comprises:
a P-type semiconductor substrate;
an N-type well, disposed in said P-type semiconductor substrate;
a P-type well, disposed in said N-type well;
a transistor, disposed on the surface of said P-type well, and having a first electrically-conductive gate and a plurality of first ion-doped regions, said first ion-doped regions separately disposed at both sides of said first electrically-conductive gate and respectively functioning as the source and the drain; and
a capacitor structure, disposed on the surface of said P-type well, and having a second electrically-conductive gate and a second ion-doped region; wherein said first electrically-conductive gate and said second electrically-conductive gate being electrically interconnected to form a single floating gate;
wherein said operation method is characterized in:
a substrate voltage Vsub, a source voltage Vs, a drain voltage Vd, a P-type well voltage Vpwell, an N-type well voltage Vnwell, and a control gate voltage Vc are respectively applied to said P-type semiconductor substrate, said source, said drain, said P-type well, said N-type well and said second ion-doped region, and said voltages meet the following conditions:
in writing said memory:
Vc>Vs>Vpwell, and
Vd>Vs>Vpwell, and
Vsub is grounded, and
Vnwell≧0; and
in erasing said memory:
Vc>Vs≧Vpwell, and
Vd>Vs≧Vpwell, and
Vsub is grounded, and
Vnwell≧0.