Modulation methods and systems

A modulation system for modulating symbols in a frame of a compact disc, the modulation system comprising:

• a code table for converting a plurality of data words into code words for corresponding data symbols;
• a Run Length Limited (RLL) checking device for receiving a plurality of combinations of potential merge bits to be inserted between successive symbols of the frame and for generating at least one combination of candidate merge bits according to the plurality of combinations of potential merge bits, a data symbol immediately preceding the location of the candidate merge bits, and a data symbol immediately succeeding the location of the candidate merge bits, wherein each combination of candidate merge bits satisfies a predetermined run length restriction on bits contained in the frame;
• and
• a digital sum value (DSV) controller, wherein when a group of possible combinations of candidate merge bits is detected, the DSV controller calculates a cumulative DSV for each combination of candidate merge bits, selects the combination of candidate merge bits which minimizes (optimizes) the absolute cumulative DSV when a subsequent group of possible combinations of candidate merge bits is detected or after a predetermined delay, and inserts the selected combination of candidate merge bits between the two successive data symbols.

A modulation method for symbols in a frame of a compact disc, comprising the steps of:

• receiving a plurality of data words;
• modulating each data word into a code word of a corresponding data symbol;
• providing a plurality of combinations of potential merge bits to be inserted between successive symbols of the frame;
• generating at least one combination of candidate merge bits according to the plurality of combinations of potential merge bits, a data symbol immediately preceding the location of the candidate merge bits, and a data symbol immediately succeeding the location of the candidate merge bits, wherein each combination of candidate merge bits satisfies a Modified Run Length Limited (MRLL) 1-10 rule stipulating that binary ones are separated by a minimum of one and a maximum of ten binary zeroes;
• and
• when a group of possible combinations of candidate merge bits is detected:
• calculating a cumulative digital sum value (DSV) for each combination of candidate merge bits;
• selecting the combination of candidate merge bits which minimizes (optimizes) the absolute cumulative DSV when a subsequent group of possible combinations of candidate merge bits is detected or after a predetermined delay;
• and
• inserting the selected combination of candidate merge bits between the two successive data symbols.