Three inch silicon carbide wafer with low warp, bow, and TTV
AssigneeCree, Inc.
InventorsAdrian Powell, William H. Brixius, Robert Tyler Leonard, Davis Andrew McClure, Michael Laughner
Life of this patent
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Abstract
A high quality single crystal wafer of SiC is disclosed. The wafer has a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow less than about 5 μm, and a total thickness variation of less than about 2.0 μm.
Claims17
A high quality single crystal wafer of SiC having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm and a TTV of less than about 2.0 μm.
A high quality semiconductor wafer comprising:
- a silicon carbide wafer having a diameter of at least about 3 inches;
- said wafer having the 4H polytype;
- and
- said wafer having a warp of between about 0.05 μm and about 5 μm, a bow of between about 0.05 μm and about 5 μm, and a TTV of between about 0.5 and 2.0 μm.
A high quality semiconductor precursor wafer comprising:
- a silicon carbide wafer having a diameter of at least about 3 inches;
- said wafer having a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm;
- and
- at least one epitaxial layer on said surface of said silicon carbide wafer selected from the group consisting of Group III-nitrides and silicon carbide.
A semiconductor device precursor structure comprising:
- a silicon carbide wafer having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm;
- and
- a plurality of respective Group III-nitride epitaxial layers on some portions of said wafer.
A semiconductor wafer comprising:
- a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another;
- and
- a plurality of devices on said silicon carbide substrate, each said device comprising:
- an epitaxial layer located on the substrate, said layer having a concentration of suitable dopant atoms for making the epitaxial layer a first conductivity type, and respective source, channel, and drain portions;
- a metal oxide layer on said channel portion;
- and
- a metal gate contact on said metal oxide layer for forming an active channel when a bias is applied to said metal gate contact.
A semiconductor wafer comprising:
- a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another;
- and
- a plurality of devices on said silicon carbide substrate, each said device comprising:
- a conductive channel on said substrate;
- a source and a drain on said conductive channel;
- and
- a metal gate contact between said source and said drain on said conductive channel for forming an active channel when a bias is applied to said metal gate contact.
A semiconductor wafer comprising:
- a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another;
- and
- a plurality of junction field-effect transistors positioned on said single crystal silicon carbide substrate.
A semiconductor wafer comprising:
- a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another;
- and
- a plurality of hetero-field effect transistors positioned on said single crystal silicon carbide substrate.
A semiconductor wafer comprising:
- a bulk single crystal silicon carbide substrate having a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow of less than about 5 μm, and a TTV of less than about 2.0 μm, said bulk single crystal having respective first and second surfaces opposite one another;
- and
- a plurality of diodes positioned on said single crystal silicon carbide substrate.
Dependencies are inferred from the claim text.