# US 7,412,672 B1 · Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

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- Number: US 7,412,672 B1
- Document ID: US7412672B1
- Status: Granted
- Kind: B1
- Application number: 11/104,651
- Filed: 2005-04-13
- Granted: 2008-08-12
- Earliest claimed: 2002-01-16
- Assignees: Syntest Technologies, Inc.
- Inventors: Laung-Terng Wang; Xiaoqing Wen; Shyh-Horng Lin; Khader S. Abdel-Hafez
- Web page: https://patentgrep.com/patent/US7412672B1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/31926: {Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing}
- G01R 31/318533: {using scanning techniques, e.g. LSSD, Boundary Scan, JTAG}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.

## Claims

### Claim 1

A method for generating broadcast scan patterns to test a scan-based integrated circuit through a broadcaster and a compactor, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs connected to the broadcaster, the scan chain outputs connected to the compactor, said method comprising the steps of:
a) compiling the HDL (hardware description language) code modeled at gate-level that represents said scan-based integrated circuit, said broadcaster, and said compactor into a sequential circuit model;
b) establishing a set of input constraints on first selected scan cells based on the predetermined values to be assigned on said broadcaster and second selected scan cells based on the predetermined values to be assigned on said compactor during each shift cycle or between test sessions;
c) transforming said sequential circuit model into an equivalent combinational circuit model by further duplicating or expanding said broadcaster into third selected scan cells and said compactor into fourth selected scan cells in said equivalent combinational circuit model;
d) generating said broadcast scan patterns according to said set of input constraints to avoid X-impact and aliasing; and
e) re-assigning a new set of input constraints and repeating step (d) until a predetermined limiting criterion is met,
wherein said broadcaster is selectively an LFSR (linear-feedback shift register) based sequential circuit, or a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above; and wherein said compactor is selectively an XOR network comprising one or more XOR gates, and
wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit.

### Claim 2 (depends on 1)

The method of claim 1, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing random-pattern fault simulation on said equivalent combinational circuit model using a selected set of random patterns as said broadcast scan patterns.

### Claim 3 (depends on 1)

The method of claim 1, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing combinational ATPG (automatic test pattern generation) on said equivalent combinational circuit model to generate said broadcast scan patterns.

### Claim 4 (depends on 1)

The method of claim 1, further comprising finding an optimal scan order to minimize the inter-dependency of selected scan cells in a selected scan chain on other selected scan cells in other selected scan chains to be positioned on the same shift cycle.

### Claim 5 (depends on 4)

The method of claim 4, wherein said finding an optimal scan order further comprises reordering said selected scan cells in said selected scan chains according to said optimal scan order.

### Claim 6 (depends on 5)

The method of claim 5, wherein said finding an optimal scan order further comprises inserting one or more spare scan cells into a said selected scan chain to further minimize or eliminate the inter-dependency of said selected scan chain on other selected scan chains.

### Claim 7 (depends on 1)

The method of claim 1, further comprising generating HDL test benches as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit using simulation methods.

### Claim 8 (depends on 1)

The method of claim 1, further comprising generating ATE (automatic test equipment) test programs as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster, said compactor, and said scan-based integrated circuit in said ATE.

### Claim 9 (depends on 1)

The method of claim 1, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

### Claim 10 (depends on 1)

The method of claim 1, wherein said broadcaster further comprises using a virtual scan controller to control said LFSR based sequential circuit or said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

### Claim 11 (depends on 10)

The method of claim 10, wherein said virtual scan controller further comprises one or more buffers or inverters.

### Claim 12 (depends on 10)

The method of claim 10, wherein said virtual scan controller is a decoder.

### Claim 13 (depends on 10)

The method of claim 10, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

### Claim 14 (depends on 13)

The method of claim 13, wherein said virtual scan controller is a shift register.

### Claim 15 (depends on 1)

The method of claim 1, wherein said broadcast scan patterns are chosen to test manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, in said scan-based integrated circuit.

### Claim 16

A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster and a compactor, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs connected to the broadcaster, the scan chain outputs connected to the compactor, said method comprising the steps of:
a) compiling the HDL (hardware description language) code modeled at register-transfer level (RTL) or gate-level that represents said scan-based integrated circuit, said broadcaster, and said compactor into a sequential circuit model;
b) establishing a set of input constraints on first selected scan cells based on the predetermined values to be assigned on said broadcaster and second selected scan cells based on the predetermined values to be assigned on said compactor during each shift cycle or between test sessions;
c) transforming said sequential circuit model into an equivalent combinational circuit model by further duplicating or expanding said broadcaster into third selected scan cells and said compactor into fourth selected scan cells in said equivalent combinational circuit model;
d) generating said broadcast scan patterns according to said set of input constraints to avoid X-impact and aliasing; and
e) re-assigning a new set of input constraints and repeating step (d) until a predetermined limiting criterion is met,
wherein said broadcaster is selectively an LFSR (linear-feedback shift register) based sequential circuit, or a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above; and wherein said compactor is selectively an XOR network comprising one or more XOR gates, and
wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit.

### Claim 17 (depends on 16)

The computer-readable memory of claim 16, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing random-pattern fault simulation on said equivalent combinational circuit model using a selected set of random patterns as said broadcast scan patterns.

### Claim 18 (depends on 16)

The computer-readable memory of claim 16, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing combinational ATPG (automatic test pattern generation) on said equivalent combinational circuit model to generate said broadcast scan patterns.

### Claim 19 (depends on 16)

The computer-readable memory of claim 16, further comprising finding an optimal scan order to minimize the inter-dependency of selected scan cells in a selected scan chain on other selected scan cells in other selected scan chains to be positioned on the same shift cycle.

### Claim 20 (depends on 19)

The computer-readable memory of claim 19, wherein said finding an optimal scan order further comprises reordering said selected scan cells in said selected scan chains according to said optimal scan order.

### Claim 21 (depends on 20)

The computer-readable memory of claim 20, wherein said finding an optimal scan order further comprises inserting one or more spare scan cells into a said selected scan chain to further minimize or eliminate the inter-dependency of said selected scan chain on other selected scan chains.

### Claim 22 (depends on 16)

The computer-readable memory of claim 16, further comprising generating HDL test benches as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit using simulation methods.

### Claim 23 (depends on 16)

The computer-readable memory of claim 16, further comprising generating ATE (automatic test equipment) test programs as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster, said compactor, and said scan-based integrated circuit in said ATE.

### Claim 24 (depends on 16)

The computer-readable memory of claim 16, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

### Claim 25 (depends on 16)

The computer-readable memory of claim 16, wherein said broadcaster further comprises using a virtual scan controller to control said LFSR based sequential circuit or said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

### Claim 26 (depends on 25)

The computer-readable memory of claim 25, wherein said virtual scan controller further comprises one or more buffers or inverters.

### Claim 27 (depends on 25)

The computer-readable memory of claim 25, wherein said virtual scan controller is a decoder.

### Claim 28 (depends on 25)

The computer-readable memory of claim 25, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

### Claim 29 (depends on 28)

The computer-readable memory of claim 28, wherein said virtual scan controller is a shift register.

### Claim 30 (depends on 16)

The computer-readable memory of claim 16, wherein said broadcast scan patterns are chosen to test manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, in said scan-based integrated circuit.

### Claim 31

An electronic design automation system comprising:
a processor;
a bus coupled to said processor; and
a computer-readable memory coupled to said bus and having computer-readable program code stored therein for causing said electronic design automation system to perform a method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster and a compactor, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs connected to the broadcaster, the scan chain outputs connected to the compactor, said method comprising the steps of:
a) compiling the HDL (hardware description language) code modeled at register-transfer level (RTL) or gate-level that represents said scan-based integrated circuit, said broadcaster, and said compactor into a sequential circuit model;
b) establishing a set of input constraints on first selected scan cells based on the predetermined values to be assigned on said broadcaster and second selected scan cells based on the predetermined values to be assigned on said compactor during each shift cycle or between test sessions;
c) transforming said sequential circuit model into an equivalent combinational circuit model by further duplicating or expanding said broadcaster into third selected scan cells and said compactor into fourth selected scan cells in said equivalent combinational circuit model;
d) generating said broadcast scan patterns according to said set of input constraints to avoid X-impact and aliasing; and
e) re-assigning a new set of input constraints and repeating step (d) until a predetermined limiting criterion is met,
wherein said broadcaster is selectively an LFSR (linear-feedback shift register) based sequential circuit, or a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above; and wherein said compactor is selectively an XOR network comprising one or more XOR gates, and
wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit.

### Claim 32 (depends on 31)

The system of claim 31, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing random-pattern fault simulation on said equivalent combinational circuit model using a selected set of random patterns as said broadcast scan patterns.

### Claim 33 (depends on 31)

The system of claim 31, wherein said generating said broadcast scan patterns according to said set of input constraints further comprises performing combinational ATPG (automatic test pattern generation) on said equivalent combinational circuit model to generate said broadcast scan patterns.

### Claim 34 (depends on 31)

The system of claim 31, further comprising finding an optimal scan order to minimize the inter-dependency of selected scan cells in a selected scan chain on other selected scan cells in other selected scan chains to be positioned on the same shift cycle.

### Claim 35 (depends on 34)

The system of claim 34, wherein said finding an optimal scan order further comprises reordering said selected scan cells in said selected scan chains according to said optimal scan order.

### Claim 36 (depends on 35)

The system of claim 35, wherein said finding an optimal scan order further comprises inserting one or more spare scan cells into a said selected scan chain to further minimize or eliminate the inter-dependency of said selected scan chain on other selected scan chains.

### Claim 37 (depends on 31)

The system of claim 31, further comprising generating HDL test benches as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster and said scan-based integrated circuit using simulation methods.

### Claim 38 (depends on 31)

The system of claim 31, further comprising generating ATE (automatic test equipment) test programs as said virtual scan patterns, according to said broadcast scan patterns, to verify correctness of said broadcaster, said compactor, and said scan-based integrated circuit in said ATE.

### Claim 39 (depends on 31)

The system of claim 31, wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

### Claim 40 (depends on 31)

The system of claim 31, wherein said broadcaster further comprises using a virtual scan controller to control said LFSR based sequential circuit or said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

### Claim 41 (depends on 40)

The system of claim 40, wherein said virtual scan controller further comprises one or more buffers or inverters.

### Claim 42 (depends on 40)

The system of claim 40, wherein said virtual scan controller is a decoder.

### Claim 43 (depends on 40)

The system of claim 40, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

### Claim 44 (depends on 43)

The system of claim 43, wherein said virtual scan controller is a shift register.

### Claim 45 (depends on 31)

The system of claim 31, wherein said broadcast scan patterns are chosen to test manufacturing faults, including stuck-at faults, transition faults, path-delay faults, IDDQ (IDD quiescent current) faults, and bridging faults, in said scan-based integrated circuit.

### Claim 46

A method that synthesizes a broadcaster and a compactor to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs coupled to the broadcaster and the scan chain outputs coupled to the compactor, said method comprising the steps of:
a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;
b) establishing constraints on said broadcaster, said compactor, and for stitching;
c) synthesizing said broadcaster according to said constraints specified on said broadcaster;
d) synthesizing said compactor according to said constraints specified on said compactor;
e) stitching said broadcaster and said compactor on said sequential circuit model according to said constraints specified for stitching; and
f) generating synthesized HDL code modeled at RTL or gate-level,
wherein said broadcaster is selectively an LFSR (linear-feedback shift register) based sequential circuit, or a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above, and
wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit.

### Claim 47 (depends on 46)

The method of claim 46, wherein said broadcaster further comprises removing selected scan cells from selected scan chains and re-stitching said selected scan cells in said selected scan chains according to said constraints specified on said broadcaster.

### Claim 48 (depends on 46)

The method of claim 46, wherein said broadcaster is said a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above.

### Claim 49 (depends on 48)

The method of claim 48, wherein said broadcaster further comprises using a plurality of said scan connectors to connect the outputs of said combinational logic network to selected scan chain inputs in said scan-based integrated circuit, wherein said plurality of scan connectors include one or more buffers, inverters, lockup elements each comprising an inverter and a memory element such as D flip-flop or D latch, spare scan cells, multiplexers, or any combination of the above.

### Claim 50 (depends on 48)

The method of claim 48, wherein said broadcaster further comprises using a virtual scan controller to control said combinational logic network, wherein said virtual scan controller controls the operation of said broadcaster during each shift cycle or between test sessions.

### Claim 51 (depends on 50)

The method of claim 50, wherein said virtual scan controller further comprises one or more buffers or inverters.

### Claim 52 (depends on 50)

The method of claim 50, wherein said virtual scan controller is a decoder.

### Claim 53 (depends on 50)

The method of claim 50, wherein said virtual scan controller is a finite-state machine containing one or more memory elements, such as D flip-flops or D latches, wherein said finite-state machine is loaded with a predetermined state before a test session starts.

### Claim 54 (depends on 53)

The method of claim 53, wherein said virtual scan controller is a shift register.

### Claim 55 (depends on 46)

The method of claim 46, wherein said broadcaster is selectively placed within said scan-based integrated circuit, inside said ATE, or between said ATE and said scan-based integrated circuit.

### Claim 56 (depends on 46)

The method of claim 46, wherein said compactor is selectively an XOR network or a multiple-input signature register (MISR), wherein said multiple-input signature register (MISR) further comprises a plurality of XOR gates and a plurality of memory elements, such as D flip-flops or D latches.

### Claim 57 (depends on 46)

The method of claim 46, wherein said compactor further comprises using a mask network to enable or disable testing or diagnosis of selected scan cells in selected scan chains, wherein said mask network includes one or more AND gates.

### Claim 58 (depends on 46)

The method of claim 46, wherein said compactor is selectively placed within said scan-based integrated circuit, inside said ATE, or between said ATE and said scan-based integrated circuit.