# US 7,412,624 B1 · Methods and apparatus for debugging a system with a hung data bus

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- Number: US 7,412,624 B1
- Document ID: US7412624B1
- Status: Granted
- Kind: B1
- Application number: 10/940,936
- Filed: 2004-09-14
- Granted: 2008-08-12
- Earliest claimed: 2004-09-14
- Assignees: Altera Corporation
- Inventors: Andrew Draper
- Web page: https://patentgrep.com/patent/US7412624B1

## CPC

- G01R 31/318583: {Design for test}
- G01R 31/31705: {Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544)}
- G01R 31/318591: {Tools}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Methods and apparatus are provided to facilitate debugging of a system with a hung data bus. A register scan chain is used to read data from logic blocks of the hung system. The scan chain is also used to write data into the logic blocks, possibly resetting a subset of those blocks or otherwise causing them to exit the hung state. The resetting may terminate the hung instruction in a manner that allows subsequent instructions to be executed, including entry into debug mode.

## Claims

### Claim 1

Circuitry for forcing an integrated circuit out of a hung state, comprising:
at least one logic block implemented on the integrated circuit; and
at least one shift register circuit implemented on the integrated circuit, associated with the at least one logic block, wherein:
the at least one shift register circuit can write control data to the at least one logic block; and
each of the at least one logic block can reset itself responsive to the value of the control data.

### Claim 2 (depends on 1)

The circuitry of claim 1, further wherein:
the at least one shift register circuit can read status data from the at least one logic block.

### Claim 3 (depends on 2)

The circuitry of claim 2, wherein:
the status data comprises memory address data.

### Claim 4 (depends on 2)

The circuitry of claim 2, wherein:
the status data comprises data indicating a status of at least one first-in-first-out (“FIFO”) queue.

### Claim 5 (depends on 2)

The circuitry of claim 2, wherein:
the status data comprises data indicating a status of at least one internal signal within the at least one logic block.

### Claim 6 (depends on 1)

The circuitry of claim 1, wherein:
each of the at least one logic block is configured to reset itself responsive to a value of 1 in the control data.

### Claim 7 (depends on 1)

The circuitry of claim 1, wherein:
each of the at least one block is configured to release itself from a hung state responsive to a value of 1 in the control data.

### Claim 8 (depends on 1)

The circuitry of claim 1, wherein:
the at least one logic block comprises a microprocessor and bridge circuitry.

### Claim 9 (depends on 8)

The circuitry of claim 8, wherein:
resetting at least part of the bridge circuitry can release the microprocessor from a hung state.

### Claim 10 (depends on 9)

The circuitry of claim 9, wherein:
the hung state results from an unterminated read request issued from the microprocessor through the bridge circuitry.

### Claim 11 (depends on 1)

The circuitry of claim 1, further comprising:
JTAG logic circuitry connected to the at least one shift register circuit.

### Claim 12 (depends on 11)

The circuitry of claim 11, wherein:
the JTAG logic circuitry can provide the control data for the at least one shift register circuit.

### Claim 13 (depends on 12)

The circuitry of claim 12, wherein:
the JTAG logic circuitry can accept the status data from the at least one shift register circuit.

### Claim 14 (depends on 11)

The circuitry of claim 11, further comprising:
a JTAG cable connected to the JTAG logic circuitry; and
a host computer connected to the JTAG cable.

### Claim 15 (depends on 1)

An integrated circuit, comprising the circuitry of claim 1.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the integrated circuit comprises:
an ASIC portion; and
a PLD portion.

### Claim 17 (depends on 15)

A printed circuit board, comprising the integrated circuit of claim 15.

### Claim 18 (depends on 16)

A data processing system, comprising the printed circuit board of claim 16.

### Claim 19

A method of forcing an integrated circuit out of a hung state, comprising:
reading status data from at least one logic block implemented on the integrated circuit to at least one shift register implemented on the integrated circuit;
shifting the status data out of the at least one shift register;
shifting control data into the at least one shift register; and
writing the control data from the at least one shift register to the at least one logic block.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the writing is capable of resetting each of the at least one logic block, responsive to the control data.

### Claim 21 (depends on 20)

The method of claim 20, wherein:
resetting the at least one logic block can terminate a read instruction.

### Claim 22 (depends on 19)

The method of claim 19, wherein:
the shifting the status data and the shifting the control data occur simultaneously.

### Claim 23 (depends on 19)

The method of claim 19, wherein:
the status data is processed by JTAG logic circuitry; and
the control data is transferred from JTAG logic circuitry.

### Claim 24 (depends on 19)

The method of claim 19, further comprising:
resetting the at least one logic block to release the integrated circuit from a hung state; and
executing an instruction to enter debug mode.

### Claim 25

Circuitry for reading status data from an integrated circuit and writing control data to the integrated circuit, comprising:
means for reading the status data from at least one logic block implemented on the integrated circuit; and
means for writing the control data from at least one shift register implemented on the integrated circuit to the at least one logic block, wherein:
the reading and writing can be performed while the integrated circuit is in a hung state; and
the writing can release the integrated circuit from the hung state.

### Claim 26 (depends on 25)

The circuitry of claim 25, wherein the at least one logic block comprises:
a microprocessor; and
a peripheral connected to the microprocessor.

### Claim 27 (depends on 26)

The circuitry of claim 26, wherein:
the integrated circuit enters the hung state after processing a read request from the microprocessor to the peripheral.

### Claim 28 (depends on 25)

The circuitry of claim 25, further comprising:
means for controlling the reading and writing using a JTAG protocol; and
means for entering a JTAG debug mode after releasing the integrated circuit from the hung state.