# US 7,412,618 B2 · Combined alignment scrambler function for elastic interface

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- Number: US 7,412,618 B2
- Document ID: US7412618B2
- Status: Granted
- Kind: B2
- Application number: 11/055,817
- Filed: 2005-02-11
- Published: 2006-08-31
- Granted: 2008-08-12
- Earliest claimed: 2005-02-11
- Assignees: International Business Machines Corporation
- Inventors: Frank D. Ferraiolo; Robert J. Reese; Michael B. Spear
- Web page: https://patentgrep.com/patent/US7412618B2

## CPC

- H04L 25/14: Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver}
- H04L 7/0037: {Delay of clock signal}
- H04L 7/005: {Correction by an elastic buffer}
- H04L 7/10: Arrangements for initial synchronisation
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04L 7/044: {using a single bit, e.g. start stop bit}
- H04L 7/046: {using a dotting sequence}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.

## Claims

### Claim 1

A method of de-skewing a plurality of data bits transmitted over an elastic interface bus comprising the steps of:
encoding an IAP training pattern with a first data bit, wherein the step of encoding results in a scrambled pattern, wherein the first data bit is one of the plurality of data bits;
transmitting the scrambled pattern from a driver to a receiver, wherein the step of transmitting a scrambled pattern results in a transmitted scrambled pattern;
transmitting a first clock signal from the driver to the receiver;
receiving the transmitted scrambled pattern at the receiver, resulting in a received scrambled pattern, wherein the received scrambled pattern comprises a plurality of data eyes;
receiving the first clock signal at the receiver, resulting in a received first clock signal, wherein the received first clock signal comprises a plurality of clock edges;
delaying the received scrambled pattern by less than a bit time to align centers of the plurality of data eyes with a plurality of nearest of the plurality of clock edges; and
decoding the scrambled pattern using the IAP training pattern, wherein the step of decoding results in a decoded training pattern and a decoded data bit;
wherein the IAP pattern has a plurality of attributes including:
a number X of beats;
a plurality of isolated ‘1’s;
a plurality of isolated ‘0’s;
a plurality of instances in which consecutive beats in the IAP pattern equal 01010;
one instance of a timing pattern; and
combining the values of every Nth data beat equals a recognizable pattern, wherein the recognizable pattern includes a single 1 and a plurality of ‘0’s.