# US 7,412,613 B2 · Integrated circuit devices that support dynamic voltage scaling of power supply voltages

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- Number: US 7,412,613 B2
- Document ID: US7412613B2
- Status: Granted
- Kind: B2
- Application number: 11/060,838
- Filed: 2005-02-18
- Published: 2005-08-25
- Granted: 2008-08-12
- Earliest claimed: 2004-02-20
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Gi-ho Park
- Web page: https://patentgrep.com/patent/US7412613B2

## CPC

- G06F 1/3296: by lowering the supply or operating voltage
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An integrated circuit device is provided with a power supply voltage generator therein. This voltage generator is configured to respond to an operating mode control signal by generating first and second power supply voltages at equivalent voltage levels when the operating mode control signal designates a normal mode of operation within the integrated circuit device. The power supply voltage generator is also configured to reduce the first and second power supply voltages to unequal lower voltage levels when the operating mode control signal designates a power saving mode of operation within the integrated circuit device. The power supply voltage generator may also generate a third power supply voltage at a constant level during both the normal and power saving modes of operation.

## Claims

### Claim 1

An integrated circuit device, comprising:
a power supply voltage generator configured to respond to an operating mode control signal by generating first and second power supply voltages at equivalent voltage levels when the operating mode control signal designates a normal mode of operation within the integrated circuit device and reducing the first power supply voltage to a positive voltage less than the second power supply voltage, which remains constant, when the operating mode control signal designates a power saving mode of operation within the integrated circuit device;
a first operating circuit powered by the first power supply voltage during the normal and power saving modes of operation; and
a second operating circuit powered by the second power supply voltage during the normal and power saving modes of operation and responsive to the operating mode control signal, said second operating circuit configured to support a power saving mode of operation by replacing a first internal data path therein with a second internal data path when the operating mode control signal switches from designating the normal mode of operation to designating the power saving mode of operation; and
wherein said second operating circuit is further configured to utilize an additional timing margin resulting from a higher frequency of operation of the second operating circuit relative to the first operating circuit during the power saving mode of operation, when performing a backup access to the first internal data path in response to detecting a read data failure associated with the second internal data path.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein said second operating circuit comprises a cache memory and a line buffer in the internal data path; and wherein said second operating circuit is configured to replace the cache memory with the line buffer when the operating mode control signal switches from designating the normal mode of operation to designating the power saving mode of operation.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, wherein said second operating circuit operates at a higher frequency than said first operating circuit during the power saving mode of operation.

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, wherein said second operating circuit comprises at least one memory enable circuit responsive to the operating mode control signal.

### Claim 5 (depends on 1)

The integrated circuit device of claim 1, wherein the third operating integrated circuit comprises:
a cache memory responsive to an address;
a line buffer responsive to the address;
a cache memory enable circuit coupled to the cache memory and responsive to the operating mode control signal; and
a line buffer enable circuit coupled to the line buffer and responsive to the operating mode control signal.

### Claim 6 (depends on 5)

The integrated circuit device of claim 5, wherein the line buffer is configured to generate an output control signal; and wherein the cache memory enable circuit is responsive to the output control signal.