# US 7,412,570 B2 · Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state

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- Number: US 7,412,570 B2
- Document ID: US7412570B2
- Status: Granted
- Kind: B2
- Application number: 11/351,058
- Filed: 2006-02-09
- Published: 2007-06-07
- Granted: 2008-08-12
- Earliest claimed: 2005-11-15
- Assignees: Sun Microsystems, Inc.; Sun Microsystems Technology Ltd.
- Inventors: Laurent R. Moll; Yu Qing Cheng; Peter N. Glaskowsky; Seungyoon Peter Song
- Web page: https://patentgrep.com/patent/US7412570B2

## CPC

- G06F 12/0835: {for main memory peripheral accesses (e.g. I/O or DMA)}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 2212/1028: Power efficiency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).

## Claims

### Claim 1

A method including the steps of:
pre-filling, in response to a transition request for a processor to enter a snooping-disabled mode, a buffer/mini-cache with data from the processor;
allowing, after the pre-filling, the processor to enter the snooping-disabled mode;
providing, while the processor is in the snooping-disabled mode, a first portion of the data from the buffer/mini-cache to a direct memory access (dma) device in response to a dma read request from the dma device, and
modifying a second portion of the data in the buffer/mini-cache in response to a dma write request from the dma device;
flushing, in response to a transition request for the processor to exit the snooping-disabled mode, the second portion of the data to the processor; and
allowing, after the flushing, the processor to exit the snooping-disabled mode.

### Claim 2 (depends on 1)

The method of claim 1, wherein at least one of the DMA requests is a non-cacheable request.

### Claim 3 (depends on 1)

The method of claim 1, wherein at least one of the DMA requests is a cacheable request.

### Claim 4

A system including:
a microprocessor configured to access a dynamic random access read/write memory (dram);
a buffer/mini-cache coupled to the microprocessor; and
a direct memory access (dma) device;
wherein the buffer/mini-cache is configured to pre-fill data from the microprocessor in response to a transition request for the microprocessor to enter a low-power state, wherein the microprocessor is responsive to the transition request after the data is pre-filled, wherein the buffer/mini-cache is enabled to conditionally provide a first portion of the data in response to a read request from the dma device,wherein the buffer/mini-cache is enabled to conditionally modify a second portion of the data in response to a write request from the dma device, wherein the buffer/mini-cache is enabled to flush the second portion of the data to the microprocessor, and wherein the microprocessor is responsive to a transition request for the microprocessor to exit the low-power state after the buffer/mini-cache is flushed.

### Claim 5 (depends on 4)

The system of claim 4, wherein the buffer/mini-cache is enabled/configured to implement a plurality of lines, each line having a respective status field.

### Claim 6 (depends on 5)

The system of claim 5, wherein the second portion of the data is held in at least one of the lines, and the status field therein is set to a ‘dirty’ value in response to the write request.

### Claim 7 (depends on 6)

The system of claim 6, wherein the status field of the at least one line is set to a ‘free’ value in response to the flush.

### Claim 8 (depends on 7)

The system of claim 7, wherein the data is pre-filled into a group of the lines each having a respective status field value of ‘free’.

### Claim 9 (depends on 8)

The system of claim 8, wherein the respective status field of each line of the group is set to a value of ‘clean’ as the data is pre-filled.

### Claim 10 (depends on 9)

The system of claim 9, wherein that the first portion of the data is held in at least an other one of the lines, and the status field therein is left at a ‘clean’ value after the read request.

### Claim 11 (depends on 4)

The system of claim 4, further including a physical address range register that is configured to compare to a respective physical address that is specified by each of the read and the write requests.

### Claim 12 (depends on 11)

The system of claim 11, wherein the conditional providing of the first portion of the data is dependent upon the compare.

### Claim 13 (depends on 11)

The system of claim 11, wherein the conditional modifying of the second portion of the data is dependent upon the compare.

### Claim 14 (depends on 11)

The system of claim 11, wherein the physical address range register is programmable by the microprocessor.

### Claim 15 (depends on 4)

The system of claim 4, further including the dram.

### Claim 16

A method, comprising:
responding, while a coherency domain is in an incoherent mode, to selected read and write accesses by referencing a buffer/mini-cache;
pre-filling, before entry to the incoherent mode, at least a portion of the buffer/mini-cache with pre-fill data from the coherency domain; and
before the coherency domain enters a coherent mode, flushing modified information from the buffer/mini-cache to the coherency domain and marking regions of the buffer/mini-cache holding unmodified information as available for pre-filling;
wherein the responding to one of the selected read accesses includes searching the buffer/mini-cache for read data to satisfy the one of the read accesses, and the responding to one of the selected write accesses includes searching the buffer/mini-cache for a location to store write data provided by the one of the write accesses.

### Claim 17 (depends on 16)

The method of claim 16, wherein the selected read and write accesses are a subset of device accesses provided by a device, and the subset is determined at least in part by comparing a respective physical address associated with each of the device accesses with at least one physical address register.

### Claim 18 (depends on 16)

The method of claim 16, wherein the selected read and write accesses are a subset of device accesses provided by a plurality of devices, and the subset is determined at least in part by comparing a respective device identifier associated with each of the device accesses with at least one device identification register.

### Claim 19 (depends on 16)

The method of claim 16, wherein the coherency domain includes at least one of a processor, a cache, and a link enabled to communicate with a chipset.

### Claim 20 (depends on 19)

The method of claim 19, wherein the buffer/mini-cache is implemented in the chipset.