# US 7,412,569 B2 · System and method to track changes in memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,412,569 B2 - Document ID: US7412569B2 - Status: Granted - Kind: B2 - Application number: 10/410,261 - Filed: 2003-04-10 - Published: 2004-10-14 - Granted: 2008-08-12 - Earliest claimed: 2003-04-10 - Assignees: Intel Corporation - Inventors: Alon Naveh; Abraham Mendelson - Web page: https://patentgrep.com/patent/US7412569B2 ## CPC - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a tracking list with an address and/or a corresponding address to be updated of a changed entry in an intermediate memory. A system in accordance with an exemplary embodiment of the invention may include, for example, a tracking unit to track the locations of potential data discrepancies between a reference memory and an intermediate memory. ## Claims ### Claim 1 An apparatus comprising: a processor associated with an intermediate memory and a reference memory; and a tracking unit, operably coupled to said processor, storing a variable-size list of addresses of the reference memory corresponding to addresses of one or more changed entries in the intermediate memory, wherein the size of the variable-size list of addresses corresponds to the number of said one or more changed entries, and wherein the processor writes the contents of said intermediate memory exclusive of the contents of said reference memory, wherein updates are only sent from said intermediate memory to said reference memory when a predefined criterion is met, and wherein said reference memory and said intermediate memory arc accessible exclusively by said processor. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein said tracking unit comprises: a tracking list storing said list of addresses; and a tracking controller updating said tracking list. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein said processor writes entries of said reference memory based on said list of addresses. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein said intermediate memory comprises a level-1 cache memory. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein said reference memory comprises a level-2 cache memory. ### Claim 6 A processing platform comprising: a processor; an intermediate memory operatively associated with said processor; a reference memory operatively associated with said processor; and a tracking unit, operably coupled to said processor, storing a variable-size list of addresses of said reference memory corresponding to addresses of one or more changed entries in said intermediate memory, wherein the size of the variable-size list of addresses corresponds to the number of said one or more changed entries, and wherein the processor writes the contents of said intermediate memory exclusive of the contents of said reference memory, wherein updates are only sent from said intermediate memory to said reference memory when a predefined criterion is met, and wherein said reference memory and said intermediate memory are accessible exclusively by said processor. ### Claim 7 (depends on 6) The processing platform of claim 6, wherein said tracking unit comprises: a tracking list storing said list of addresses; and a tracking controller updating said tracking list. ### Claim 8 (depends on 6) The processing platform of claim 6, wherein said processor modifies entries of said reference memory based on said list of addresses. ### Claim 9 (depends on 6) The processing platform of claim 6, wherein said intermediate memory comprises a level-1 cache memory. ### Claim 10 (depends on 6) The processing platform of claim 6, wherein said reference memory comprises a level-2 cache memory. ### Claim 11 A system comprising: a processor; an intermediate memory operatively associated with said processor; a reference memory operatively associated with said processor; a tracking unit operably coupled to said processor and storing a variable-size list of addresses of said reference memory corresponding to addresses of one or more changed entries in said intermediate memory, wherein the size of the variable-size list of addresses corresponds to the number of said one or more changed entries and wherein the processor writes the contents of said intermediate memory exclusive of the contents of said reference memory, wherein updates are only sent from said intermediate memory to said reference memory when a predefined criterion is met, and wherein said reference memory and said intermediate memory are accessible exclusively by said processor. ### Claim 12 (depends on 11) The system of claim 11, wherein said tracking unit comprises: a tracking list storing said list of addresses; and a tracking controller updating said tracking list. ### Claim 13 (depends on 11) The system of claim 11, wherein said intermediate memory comprises a level-1 cache memory. ### Claim 14 (depends on 11) The system of claim 11, wherein said reference memory comprises a level-2 cache memory. ### Claim 15 A method comprising updating a variable-size tracking list with an address of a reference memory operatively associated with a processor, which address corresponds to an address of a changed entry in an intermediate memory operatively associated with said processor, wherein the size of the variable-size tracking list corresponds to a current number of changed entries in the intermediate memory, wherein said variable-size tracking list is operably coupled to said processor, and wherein the processor writes the contents of said intermediate memory exclusive of the contents of said reference memory, wherein updates are only sent from said intermediate memory to said reference memory when a predefined criterion is met, and wherein said reference memory and said intermediate memory are accessible exclusively by said processor. ### Claim 16 (depends on 15) The method of claim 15, wherein updating the tracking list comprises writing a pointer to an address in said reference memory corresponding to the address of the changed entry in said intermediate memory. ### Claim 17 (depends on 15) The method of claim 15, wherein updating the tracking list comprises writing a pointer to the address of the changed entry in said intermediate memory corresponding to the address in said reference memory. ### Claim 18 (depends on 15) The method of claim 15, further comprising updating said reference memory based on a content of said tracking list. ### Claim 19 (depends on 15) The method of claim 15, further comprising modifying an entry in said reference memory at the address in said reference memory corresponding to the address of the changed entry in said intermediate memory. ### Claim 20 (depends on 19) The method of claim 19, further comprising changing said tracking list to reflect that the address in said reference memory has been updated. ### Claim 21 (depends on 15) The method of claim 15, further comprising updating entries in said reference memory at addresses in said reference memory corresponding to substantially all addresses of changed entries in said intermediate memory. ### Claim 22 (depends on 21) The method of claim 21, wherein updating the entries comprises updating the entries when said tracking list reaches a pre-defined percentage of its storage capacity. ### Claim 23 (depends on 21) The method of claim 21, wherein updating the entries comprises updating the entries when said intermediate memory reaches a pre-defined percentage of its storage capacity. ### Claim 24 (depends on 15) The method of claim 15, further comprising sorting said tracking list. ### Claim 25 (depends on 15) The method of claim 15, further comprising defragmenting said tracking list. ### Claim 26 (depends on 15) The method of claim 15, further comprising changing a property of said tracking list. ### Claim 27 (depends on 26) The method of claim 26, wherein changing the property of said tracking list comprises changing the size of said tracking list. ### Claim 28 (depends on 15) The method of claim 15, wherein said intermediate memory comprises a level-1 cache memory. ### Claim 29 (depends on 15) The method of claim 15, wherein said reference memory comprises a level-2 cache memory. ### Claim 30 A machine-readable medium having stored thereon a set of instructions that, if executed by a machine, cause the machine to perform a method comprising updating a variable-size tracking list with an address of a reference memory operatively associated with a processor, which address corresponds to an address of a changed entry in an intermediate memory operatively associated with said processor, wherein the size of the variable-size tracking list corresponds to a current number of changed entries in the intermediate memory, wherein said variable-size tracking list is operably coupled to said processor, and wherein the contents of said intermediate memory are written from the processor exclusive of the contents of said reference memory, wherein updates are only sent from said intermediate memory to said reference memory when a predefined criterion is met, and wherein said reference memory and said intermediate memory are accessible exclusively by said processor. ### Claim 31 (depends on 30) The machine-readable medium of claim 30, wherein the instructions that result in updating the tracking list result in storing a pointer to an address in said reference memory corresponding to the address of the changed entry in said intermediate memory. ### Claim 32 (depends on 30) The machine-readable medium of claim 30, wherein the instructions that result in updating the tracking list result in storing a pointer to the address of the changed entry in said intermediate memory corresponding to the corresponding address in said reference memory. ### Claim 33 (depends on 30) The machine-readable medium of claim 30, wherein the instructions further result in modifying said reference memory based on a content of said tracking list. ### Claim 34 (depends on 30) The machine-readable medium of claim 30, wherein the instructions further result in updating an entry in said reference memory at the address in said reference memory corresponding to the address of the changed entry in said intermediate memory. ### Claim 35 (depends on 34) The machine-readable medium of claim 34, wherein the instructions further result in updating said tracking list to indicate that the address in said reference memory has been updated. ### Claim 36 (depends on 30) The machine-readable medium of claim 30, wherein the instructions further result in updating entries in said reference memory at the addresses in said reference memory corresponding to substantially all addresses of changed entries in said intermediate memory. ### Claim 37 (depends on 36) The machine-readable medium of claim 36, wherein the instructions that result in updating the entries result in updating the entries when said tracking list reaches a pre-determined percentage of its storage capacity. ### Claim 38 (depends on 36) The machine-readable medium of claim 36, wherein the instructions that result in updating the entries result in updating the entries when said intermediate memory reaches a pre-determined percentage of its storage capacity. ### Claim 39 (depends on 30) The machine-readable medium of claim 30, wherein the instructions further result in sorting said tracking list. ### Claim 40 (depends on 30) The machine-readable medium of claim 30, wherein the instructions further result in defragmenting said tracking list. ### Claim 41 (depends on 30) The machine-readable medium of claim 30, wherein the instructions further result in modifying a property of said tracking list. ### Claim 42 (depends on 41) The machine-readable medium of claim 41, wherein the instructions that result in modifying the property of said tracking list result in modifying the size of said tracking list. ### Claim 43 (depends on 30) The machine-readable medium of claim 30, wherein said intermediate memory comprises a level-1 cache memory. ### Claim 44 (depends on 30) The machine-readable medium of claim 30, wherein said reference memory comprises a level-2 cache memory. ### Claim 45 An apparatus comprising: a processor, associated with an intermediate memory accessible exclusively by the processor and a reference memory accessible exclusively by the processor, writing the contents of the intermediate memory exclusive of the contents of the reference memory; and a tracking unit, operably coupled to said processor, updating a variable-size tracking list with an address of the reference memory, which address corresponds to an address of a changed entry in the intermediate memory, wherein the size of the variable-size tracking list corresponds to a current number of changed entries in the intermediate memory, and wherein updates are only sent from said intermediate memory to said reference memory when a predefined criterion is met. ### Claim 46 (depends on 45) The apparatus of claim 45, wherein the processor is writes a pointer to an address in said reference memory corresponding to the address of the changed entry in said intermediate memory. ### Claim 47 (depends on 45) The apparatus of claim 45, wherein the processor writes a pointer to the address of the changed entry in said intermediate memory corresponding to the address in said reference memory. ### Claim 48 (depends on 45) The apparatus of claim 45, wherein the processor updates said reference memory based on a content of said tracking list. ### Claim 49 (depends on 45) The apparatus of claim 45, wherein the processor modifies an entry in said reference memory at the address in said reference memory corresponding to the address of the changed entry in said intermediate memory. ### Claim 50 (depends on 49) The apparatus of claim 49, wherein the tracking unit changes said tracking list to reflect that the address in said reference memory has been updated. ### Claim 51 (depends on 45) The apparatus of claim 45, wherein the processor updates entries in said reference memory at addresses in said reference memory corresponding to substantially all addresses of changed entries in said intermediate memory.