# US 7,412,346 B2 · Real-time temperture detection during test > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,412,346 B2 - Document ID: US7412346B2 - Status: Granted - Kind: B2 - Application number: 11/553,616 - Filed: 2006-10-27 - Published: 2008-05-01 - Granted: 2008-08-12 - Earliest claimed: 2006-10-27 - Assignees: Intel Corporation - Inventors: Mo S. Bashir; Arun Krishnamoorthy - Web page: https://patentgrep.com/patent/US7412346B2 ## CPC - G01R 31/2874: {related to temperature} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract Apparatuses, methods, and systems associated with and/or having components capable of, detecting a temperature of an integrated circuit in real time during testing are disclosed herein. In exemplary embodiments, an integrated circuit includes a register to store a temperature limit for the integrated circuit; a temperature sensor formed on the integrated circuit to sense a temperature of the integrated circuit, and output a signal indicative of the temperature sensed, based at least in part on the temperature sensed; and testing logic coupled to the register and the temperature sensor to record a temperature violation if at any time during a testing mode of operation the temperature sensed by the temperature sensor violates the stored temperature limit. ## Claims ### Claim 1 An integrated circuit comprising: a register to store a temperature limit for the integrated circuit; a temperature sensor formed on the integrated circuit to sense a temperature of the integrated circuit, and output a signal indicative of the temperature sensed, based at least in part on the temperature sensed; testing logic coupled to the register and the temperature sensor to record a temperature violation if at any time during a testing mode of operation the temperature sensed by the temperature sensor violates the stored temperature limit; a result bit, wherein the testing logic sets the result bit to record the temperature violation; and an output pin coupled to the result bit to facilitate reading of the result bit after the test mode of operation, to determine whether the result bit was set by the testing logic during the testing mode of operation. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the register stores a minimum temperature limit, and the testing logic records the temperature violation if at any time during a testing mode of operation the temperature sensed by the temperature sensor is below the stored minimum temperature limit. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the register stores a maximum temperature limit, and the testing logic records a temperature violation if at any time during a testing mode of operation the temperature sensed by the temperature sensor is above the stored maximum temperature limit. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the integrated circuit further comprises a result bit, and the testing logic sets the result bit to record the temperature violation. ### Claim 5 (depends on 1) The integrated circuit of claim 1, further comprising another register to cooperate with the register to store a lower and an upper temperature limit of a temperature range, and the testing logic records a lower bound violation if at any time during the test mode of operation the temperature sensed is below the stored lower temperature limit, and records an upper bound violation if at any time during the testing mode of operation the temperature sensed is above the stored upper temperature limit. ### Claim 6 (depends on 5) The integrated circuit of claim 5, further comprising a processor core, and the register, the temperature sensor, and the testing logic are all disposed in the processor core. ### Claim 7 (depends on 6) The integrated circuit of claim 6, further comprising another processor core similarly constituted as said processor core at least in having a similar register, temperature sensor, and testing logic arrangement. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the test temperature limit is based at least in part on a selected one or more of a test type and a device characteristic of the integrated circuit. ### Claim 9 A method for testing an integrated circuit comprising: providing an electrical test stimulus to the integrated circuit; sensing a temperature of an interior location of the integrated circuit during said providing of the electrical test stimulus; and setting a result bit to record a temperature violation if the sensed temperature violates a temperature limit; and reading an output pin coupled to the result bit to determine whether the result bit was set during said providing the electrical test stimulus. ### Claim 10 (depends on 9) The method of claim 9, further comprising storing a minimum temperature limit, and recording the temperature violation if at any time during a testing mode of operation the temperature sensed is below the stored minimum temperature limit. ### Claim 11 (depends on 9) The method of claim 9, further comprising storing a maximum temperature limit, and recording the temperature violation if at any time during a testing mode of operation the temperature sensed is above the stored maximum temperature limit. ### Claim 12 (depends on 9) The method of claim 9, further comprising storing a lower and an upper temperature limit of a temperature range, and recording a lower bound violation if at any time during a test mode of operation the temperature sensed is below the stored lower temperature limit, and recording an upper bound violation if at any time during the test mode of operation the temperature sensed is above the stored upper temperature limit. ### Claim 13 (depends on 9) The method of claim 9, further comprising adjusting the temperature of the integrated circuit based at least in part on the temperature violation. ### Claim 14 A system comprising: an integrated circuit including: a register to store a temperature limit for the integrated circuit; a temperature sensor formed on the integrated circuit to sense a temperature of the integrated circuit, and output a signal indicative of the temperature sensed, based at least in part on the temperature sensed; testing logic coupled to the register and temperature sensor to record a temperature violation if at any time during a testing mode of operation the temperature sensed by the temperature sensor violates the stored temperature limit; a result bit, wherein the testing logic sets the result bit to record the temperature violation; and an output pin coupled to the result bit to facilitate reading of the result bit after the test mode of operation, to determine whether the result bit was set by the testing logic during the test mode of operation; and one or more mass storage devices coupled to the integrated circuit. ### Claim 15 (depends on 14) The system of claim 14, wherein the register stores a minimum temperature limit, and the testing logic records the temperature violation if at any time during a testing mode of operation the temperature sensed by the temperature sensor is below the stored minimum temperature limit. ### Claim 16 (depends on 14) The system of claim 14, wherein the register stores a maximum temperature limit, and the testing logic records a temperature violation if at any time during a testing mode of operation, the temperature sensed by the temperature sensor is above the stored maximum temperature limit. ### Claim 17 (depends on 14) The system of claim 14, further comprising another register to cooperate with the register to store a lower and an upper temperature limit of a temperature range, and the testing logic records a lower bound violation if at any time during the test mode of operation the temperature sensed is below the stored lower temperature limit, and records an upper bound violation if at any time during the test mode of operation the temperature sensed is above the stored upper temperature limit. ### Claim 18 (depends on 17) The system of claim 17, further comprising a processor core, and the register, the temperature sensor, and the testing logic are all disposed in the processor core. ### Claim 19 (depends on 18) The system of claim 18, further comprising another processor core similarly constituted as said processor core at least in having a similar register, temperature sensor, and testing logic arrangement. ### Claim 20 (depends on 14) The system of claim 14, wherein the system comprises a selected one of a server, a wireless adapter, a wireless mobile phone, a set-top box, a personal digital assistant, a tablet computing device, a laptop computing device, a desktop computing device, and an entertainment control unit.