# US 7,412,101 B2 · Semiconductor device and an image processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,412,101 B2 - Document ID: US7412101B2 - Status: Granted - Kind: B2 - Application number: 11/008,178 - Filed: 2004-12-10 - Published: 2005-07-21 - Granted: 2008-08-12 - Earliest claimed: 2003-12-12 - Assignees: Renesas Technology Corp. - Inventors: Hiromi Watanabe - Web page: https://patentgrep.com/patent/US7412101B2 ## CPC - H04N 19/423: characterised by memory arrangements (H04N19/433 takes precedence) - H04N 19/436: using parallelised computational arrangements - H04N 19/61: in combination with predictive coding - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract An apparatus for encoding a plurality of image data series and decoding a plurality of encoded image data series includes an interface control circuit for executing data read/write operation from and to a memory area, an encoding/decoding circuit for selectively executing encoding of image data of one series written into the memory area or decoding of encoded image data of one series, and a plurality of registers for giving an instruction of processing to the encoding/decoding circuit wherein the encoding/decoding circuit executes encoding and decoding on a time division basis and in a series unit for image data of a plurality of series in accordance with the instruction from the plurality of registers. The apparatus for executing encoding and decoding of multi-stream image data can be rendered compact in size. ## Claims ### Claim 1 A semiconductor device for encoding a plurality of image data series and decoding a plurality of encoded image data series, comprising: an interface control circuit which performs data read/write operation from and to a memory area; an encoding/decoding circuit which selectively performs encoding of image data of one series written into the memory area and decoding of encoded image data of one series; and a plurality of registers which provide an instruction of processing to the encoding/decoding circuit; wherein the encoding/decoding circuit performs encoding and decoding of image data of a plurality of series on a time division basis and in each series in accordance with the instruction from the plurality of registers. ### Claim 2 (depends on 1) A semiconductor device as defined in claim 1, wherein the plurality of registers include an address register, the address register is an address register to which an address of a memory area is designated for each series of image data, and the memory area is further an area to which encoding information used for encoding the image data and decoding information used for decoding the compressed image data are saved for each series of image data. ### Claim 3 (depends on 1) A semiconductor device as defined in claim 1, wherein the plurality of registers include a parameter register, the parameter register is a register to which encoding parameters read out from the memory area designated by the address register or decoding parameters are loaded, and which holds the encoding parameters written into the memory area designated by the address register or the decoding parameters. ### Claim 4 (depends on 3) A semiconductor device as defined in claim 3, wherein the plurality of registers include an encoding/decoding register, and the encoding/decoding register is a register to which encoding/decoding control information instructing as to whether encoding or decoding is to be made for the image data series is set. ### Claim 5 (depends on 4) A semiconductor device as defined in claim 4, wherein the plurality of registers include a size register and the size register is a register to which image size information instructing an image size of the image data series to be encoded or decoded to the encoding/decoding circuit is set. ### Claim 6 (depends on 5) A semiconductor device as defined in claim 5, wherein the plurality of registers include a type register and the type register is a register to which image type information instructing an image type corresponding to a prediction encoding system to the encoding/decoding circuit is set. ### Claim 7 An image processor for encoding a plurality of image data series and decoding a plurality of encoded image data series, comprising: a memory and a data processor; the data processor comprising: an interface control circuit which performs data read/write operation from and to a memory area of the memory; an encoding/decoding circuit which selectively performs encoding of image data of one series written into the memory area and decoding of encoded image data of one series; and a plurality of registers which provide an instruction of processing to the encoding/decoding circuit; wherein the encoding/decoding circuit performs encoding and decoding of image data of a plurality of series on a time division basis in each series in accordance with the instruction from the plurality of registers. ### Claim 8 (depends on 7) An image processor as defined in claim 7, wherein the plurality of register includes an address register, the address register is an address register to which an address of a memory area is designated for each series of image data, and the memory area is further an area to which encoding information used for encoding the image data and decoding information used for decoding the compressed image data are saved for each series of image data. ### Claim 9 A semiconductor device for executing encoding for a plurality of image data series, comprising: an interface control circuit for executing read/write from and to a memory area; an encoding circuit for executing encoding of image data of one series written into the memory area; and a plurality of registers for giving an instruction of processing to the encoding circuit; wherein the encoding circuit executes encoding on a time division basis and in a series unit for image data of a plurality of series in accordance with the instruction from the plurality of registers. ### Claim 10 (depends on 9) A semiconductor device as defined in claim 9, wherein the plurality of registers include an address register, and the address register is a register to which an address of a memory area is designated for each image data series, and the memory area is an area in which encoding information used for encoding the image data is saved for each series of the image data. ### Claim 11 (depends on 9) A semiconductor device as defined in claim 9, wherein the plurality of registers include a parameter register, and the parameter register is a register to which encoding parameters are loaded from the memory area designated by the address register and which holds encoding parameters to be written into the memory area designated by the address register. ### Claim 12 (depends on 11) A semiconductor device as defined in claim 11, wherein the plurality of registers include a size register and the size register is a register to which image size information instructing an image size of the image data series to be encoded is set to the encoding circuit is set. ### Claim 13 (depends on 12) A semiconductor device as defined in claim 12, wherein the plurality of registers include a type register and the type register is a register to which image type information instructing an image type corresponding to a prediction encoding system to the encoding/decoding circuit is set. ### Claim 14 An image processor for encoding a plurality of image data series, comprising: a memory and a data processor; the data processor comprising: an interface control circuit for executing read/write from and to a memory area of the memory; an encoding circuit for executing encoding of image data of one series written into the memory area; and a plurality of registers for giving an instruction of processing to the encoding circuit; wherein the encoding circuit executes encoding on a time division basis and in a series unit for image data of a plurality of series in accordance with the instruction from the plurality of registers. ### Claim 15 (depends on 14) An image processor as defined in claim 14, wherein the plurality of registers include an address register, and the address register is a register to which an address of a memory area is designated for each image data series, and the memory area is an area in which encoding information used for encoding the image data is saved for each series of the image data.