# US 7,411,969 B2 · Method, system, and apparatus for a credit based flow control in a computer system

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- Number: US 7,411,969 B2
- Document ID: US7411969B2
- Status: Granted
- Kind: B2
- Application number: 10/696,425
- Filed: 2003-10-28
- Published: 2005-04-28
- Granted: 2008-08-12
- Earliest claimed: 2003-10-28
- Assignees: Intel Corporation
- Inventors: Ling Cen
- Web page: https://patentgrep.com/patent/US7411969B2

## CPC

- H04L 47/35: by embedding flow control information in regular packets, e.g. piggybacking
- H04L 47/16: {in connection oriented networks, e.g. frame relay}
- H04L 47/39: {Credit based}
- H04L 47/50: Queue scheduling
- H04L 47/522: {Dynamic queue service slot or variable bandwidth allocation}
- H04L 47/6205: {Arrangements for avoiding head of line blocking}
- H04L 47/621: {Individual queue per connection or flow, e.g. per VC}
- H04L 49/90: Buffering arrangements
- H04L 49/901: using storage descriptor, e.g. read or write pointers
- H04L 49/9047: including multiple buffers, e.g. buffer pools
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A system, apparatus, and method for a link layer protocol to utilize a main buffer and share the remaining link units according to a list buffer or FIFO. The system includes an efficient link layer to facilitate transmitting and receiving data and information. The list buffer is used to store the buffer indexes for all the link units for the respective virtual connections.

## Claims

### Claim 1

A method for a link layer protocol comprising:
reserving a single buffer of a plurality of buffers for each of a plurality of virtual channels (VCs);
storing a plurality of buffer indexes corresponding to a plurality of buffers not reserved for each VC; and
sharing the buffers not reserved for each VC among a plurality of VCs.

### Claim 2 (depends on 1)

The method of claim 1 wherein storing the plurality of buffer indexes comprises storing the plurality of buffer indexes in a first in first out memory (FIFO).

### Claim 3 (depends on 2)

The method of claim 2 wherein the sharing remaining buffers is based at least in part on whether the buffer is used for receiving or transmitting data.

### Claim 4 (depends on 1)

The method of claim 1 wherein sharing remaining link buffers allows for switching from one list of link units for a first VC when blocked, by switching from the first VC's link buffer to the second VC's link buffer.

### Claim 5

An apparatus comprising:
a main transmit buffer and a main receiver buffer for each virtual channel (VC) for a link layer protocol of the point to point network;
a plurality of link buffers to be shared based at least in part on a link buffer list for each virtual channel; and
the main receiver and transmit buffers to be sized based at least in part on a round trip delay time.

### Claim 6 (depends on 5)

The apparatus of claim 5 wherein the apparatus is a link layer component of an electronic system.

### Claim 7 (depends on 5)

The apparatus of claim 5 wherein the apparatus facilitates the switch from a first VC's link buffer or FIFO to a second VC's link buffer or FIFO if the first VC's link buffer or FIFO is blocked.

### Claim 8

A link layer apparatus comprising:
a main transmit buffer and a main receiver buffer for each virtual channel (VC);
a main transmit buffer and a main receiver buffer for each virtual channel (VC) of the point to point network;
a sender component of a link unit coupled to send packets corresponding to a VC to indicate whether the link unit utilized a reserved credit or a shared VC buffer, the reserved credit to be utilized for another function if the shared VC buffer is used instead of the reserved credit.

### Claim 9 (depends on 8)

The link layer apparatus of claim 8 wherein the sender component facilitates a switch from a first VC's link buffer or FIFO to a second VC's link buffer or FIFO if the first VC's link buffer or FIFO is blocked.

### Claim 10

A system comprising:
at least two processors coupled into a point to point network;
a main transmit buffer and a main receiver buffer for each virtual channel (VC) of the point to point network;
a plurality of link buffers to be shared between the main transmit buffer and the main receiver buffer based at least in part on a link buffer for each virtual channel; and
a sender component of a link unit coupled to send packets corresponding to a VC to indicate whether the link unit utilized a reserved credit or a shared VC buffer, the reserved credit be utilized for another function if the shared VC buffer is used instead of the reserved credit.

### Claim 11 (depends on 10)

The system of claim 10 wherein the sender component facilitates a switch from a first VC's link buffer or FIFO to a second VC's link buffer or FIFO if the first VC's link buffer or FIFO is blocked.

### Claim 12

A system comprising:
at least two processors coupled into a point to point network;
a main transmit buffer and a main receiver buffer for each virtual channel (VC) for a link layer protocol of the point to point network;
a plurality of link buffers to be shared based at least in part on a link buffer list for each virtual channel; and
the main receiver and transmit buffers to be sized based at least in part on a round trip delay time.

### Claim 13 (depends on 12)

The system of claim 12 wherein the link layer protocol facilitates the switch from a first VC's link buffer or FIFO to a second VC's link buffer or FIFO if the first VC's link buffer or FIFO is blocked.