# US 7,411,855 B2 · Semiconductor device with improved power supply arrangement

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- Number: US 7,411,855 B2
- Document ID: US7411855B2
- Status: Granted
- Kind: B2
- Application number: 11/727,429
- Filed: 2007-03-27
- Published: 2007-08-02
- Granted: 2008-08-12
- Earliest claimed: 1998-04-10
- Assignees: Hitachi, Ltd.
- Inventors: Masashi Horiguchi; Masayuki Nakamura; Sadayuki Ohkuma; Kazuhiko Kajigaya; Yoshinobu Nakagome
- Web page: https://patentgrep.com/patent/US7411855B2

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 2207/2227: Standby or low power modes
- G11C 2211/4067: Refresh in standby or low power modes
- G11C 2211/4068: Voltage or leakage in refresh operations
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

## Claims

### Claim 1

A semiconductor device comprising:
a first memory array adapted to be selected by a first control signal and including a plurality of first memory cells and a plurality of first sense amplifiers;
a second memory array adapted to be selected by a second control signal which is different from said first control signal and including a plurality of second memory cells and a plurality of second sense amplifiers;
a power supply line provided in a mesh manner above said first and second memory arrays;
a first power supply circuit having a first output node connected to said power supply line, and adapted to receive a first voltage and to generate a second voltage; and
a second power supply circuit having a second output node connected to said power supply line, and adapted to receive said first voltage and to generate said second voltage;
wherein, during a first period in which said first memory array is selected, said first power supply circuit is adapted to output said second voltage from said first output node, and
wherein, during a second period in which the second memory array is selected after said first memory array is selected, said first power supply circuit is adapted not to output said second voltage to said first output node.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein said first control signal is a first bank control signal;
wherein said second control signal is a second bank control signal;
wherein said first memory array is a first memory bank which is adapted to respond to said first bank control signal; and
wherein said second memory array is a second memory bank which is adapted to respond to said second bank control signal.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein said second period is a period during which said first memory array is in an active standby mode.