# US 7,411,854 B2 · System and method for controlling constant power dissipation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,854 B2 - Document ID: US7411854B2 - Status: Granted - Kind: B2 - Application number: 11/406,073 - Filed: 2006-04-18 - Published: 2007-10-18 - Granted: 2008-08-12 - Earliest claimed: 2006-04-18 - Assignees: Infineon Technologies AG; Altis Semiconductor - Inventors: Ulrich Klostermann; Dietmar Gogl - Web page: https://patentgrep.com/patent/US7411854B2 ## CPC - G11C 11/16: using elements in which the storage effect is based on magnetic spin effect - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 11/2297: {Power supply circuits} - G11C 13/0038: {Power supply circuits} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell. ## Claims ### Claim 1 A method for controlling the constant power dissipation of a memory cell, the method comprising: measuring resistance of a memory cell; and controlling a source to apply a variable level of current or voltage to the memory cell, the variable level of current or voltage determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell. ### Claim 2 (depends on 1) The method of claim 1, wherein measuring the resistance of the memory cell comprises: applying a predefined current through the memory cell; and measuring a resulting voltage at the memory cell. ### Claim 3 (depends on 1) The method of claim 1, wherein measuring the resistance of the memory cell comprises: applying a predefined current through a plurality of memory cells representative of the memory cell; and measuring a resulting voltage at the plurality of representative memory cells to determine an average value of measured resistance. ### Claim 4 (depends on 1) The method of claim 1, wherein measuring the resistance of the memory cell comprises: applying a predefined voltage across the memory cell; and measuring a resulting current through the memory cell. ### Claim 5 (depends on 1) The method of claim 1, wherein measuring the resistance of the memory cell comprises: applying a predefined voltage across a plurality of memory cells representative of the memory cell; and measuring a resulting current through the plurality of representative memory cells to determine the average value of the measured resistance. ### Claim 6 (depends on 1) The method of claim 1, wherein controlling the source comprises controlling a current source to apply a variable level of current to the memory cell, the level of applied current determined in proportion to the measured resistance of the memory cell so as to result in the predefined level of power dissipation within the memory cell. ### Claim 7 (depends on 1) The method of claim 1, wherein controlling the source comprises controlling a voltage source to apply a variable voltage level to the memory cell, the level of the applied voltage determined in proportion to the measured resistance of the memory cell so as to result in the predefined level of power dissipation within the memory cell. ### Claim 8 (depends on 1) The method of claim 1, wherein controlling the source comprises controlling the source to apply said level of current or voltage for a variable duration, the variable duration determined in proportion to the predefined level of power dissipation. ### Claim 9 (depends on 1) The method of claim 1, wherein the memory cell comprises a magneto random access memory cell, and wherein the source is a current source operable to provide a write current to said magneto random access memory cell. ### Claim 10 (depends on 1) The method of claim 1, wherein the memory cell comprises a magneto random access memory cell, and wherein the source is a current source operable to provide a heating current to said magneto random access memory cell. ### Claim 11 A system configured to control constant power dissipation of a memory cell, the system comprising: means for measuring the resistance of the memory cell; and means for controlling a source to apply a variable level of current or voltage to the memory cell, the variable level of current or voltage determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell. ### Claim 12 (depends on 11) The system of claim 11, wherein the means for measuring comprises: a current source having a input for receiving a current control signal and an output coupled to the memory cell for providing a variable level of current thereto; a voltage sensor having an input coupled to the memory cell for sensing the voltage of the memory cell conducting said variable level of current and an output adapted to provide a voltage sensing signal; and a feedback circuit having an input coupled to receive the voltage sensing signal and an output for providing the current control signal. ### Claim 13 (depends on 12) The system of claim 12, wherein the current source and the voltage sensor are coupled to a cell connection line. ### Claim 14 (depends on 12) The system of claim 12, wherein the current source and the voltage sensor are coupled to a plate electrode of a CBRAM cell. ### Claim 15 (depends on 12) The system of claim 12, wherein the current source and the voltage sensor are coupled to a bit line. ### Claim 16 (depends on 11) The system of claim 11, wherein the means for measuring comprises: a current source having a input for receiving a current control signal and an output coupled to the memory cell for providing a variable level of current thereto; a voltage sensor having an input coupled to the memory cell for sensing the voltage of the memory cell conducting said variable level of current and an output adapted to provide a voltage sensing signal; a feedback circuit having an input coupled to receive the voltage sensing signal and an output for providing a feedback signal; and a timing circuit having an input coupled to receive the feedback signal and an output for providing the current control signal over a variable duration. ### Claim 17 (depends on 16) The system of claim 16, wherein the current source and the voltage sensor are coupled to a cell connection line. ### Claim 18 (depends on 16) The system of claim 16, wherein the current source and the voltage sensor are coupled to a plate electrode of a CBRAM cell. ### Claim 19 (depends on 16) The system of claim 16, wherein the current source and the voltage sensor are coupled to a bit line. ### Claim 20 A memory array, comprising: a plurality of magneto random access memory cells, each magneto random access memory cell coupled between a word line and a bit line; and a system coupled to the bit line and configured to control power dissipation of one or more memory cells coupled to said bit line, the system comprising: means for measuring resistance of the selected memory cell; and means for controlling a source to apply a variable level of current or voltage to the selected memory cell, the variable level of current or voltage determined in proportion to the measured resistance of the selected memory cell so as to result in a predefined level of power dissipation within the selected memory cell, said dissipated power operable to heat the selected memory cell. ### Claim 21 (depends on 20) The memory array of claim 20, wherein the means for measuring the resistance of the selected memory cell comprises: a current source having a input for receiving a current control signal and an output coupled to the bit line for providing a variable level of current thereto; a voltage sensor having an input coupled to the bit line for sensing the voltage of the memory cell conducting said variable level of current and an output adapted to provide a voltage sensing signal; and a feedback circuit having an input coupled to receive the voltage sensing signal and an output for providing the current control signal. ### Claim 22 (depends on 20) The memory array of claim 20, wherein the means for measuring the resistance of the selected memory cell comprises: a current source having a input for receiving a current control signal and an output coupled to the bit line for providing a variable level of current thereto; a voltage sensor having an input coupled to the bit line for sensing the voltage of the memory cell conducting said variable level of current and an output adapted to provide a voltage sensing signal; a feedback circuit having an input coupled to receive the voltage sensing signal and an output for providing a feedback signal; and a timing circuit having an input coupled to receive the feedback signal and an output for providing the current control signal over a variable duration. ### Claim 23 A computer program product, resident on a computer readable medium, operable to store executable instructions for controlling the constant power dissipation of a memory cell, the computer program product comprising: instruction code to cause measurement of the resistance of the memory cell; and instruction code to control a source to apply a variable level of current or voltage to the memory cell, the variable level of current or voltage determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell. ### Claim 24 (depends on 23) The computer program product of claim 23, wherein the instruction code to cause measurement of the resistance of the memory cell comprises: instruction code to cause application of a predefined current across the memory cell; and instruction code to cause measurement of a resultant output current through the memory cell. ### Claim 25 (depends on 23) The computer program product of claim 23, wherein the instruction code to cause measurement of the resistance of the memory cell comprises: instruction code to cause application of a predefined current across a plurality of memory cells representative of said memory cell; and instruction code to cause measurement of a resultant output current through the plurality of representative memory cells to determine an average value of the measured resistance. ### Claim 26 (depends on 23) The computer program product of claim 23, wherein the instruction code to control the source comprises instruction code to cause a current source to apply a variable level of current to the memory cell, the level of applied current determined in proportion to the measured resistance of the memory cell so as to result in the predefined level of power dissipation within the memory cell. ### Claim 27 (depends on 23) The computer program product of claim 23, wherein the instruction code to control the source comprises instruction code to cause a voltage source to apply a variable voltage level to the memory cell, the level of the applied voltage determined in proportion to the measured resistance of the memory cell so as to result in the predefined level of power dissipation within the memory cell. ### Claim 28 (depends on 23) The computer program product of claim 23, wherein the instruction code to control the source comprises instruction code to cause the source to apply said level of current or voltage for a variable duration, the variable duration determined in proportion to the predefined level of power dissipation.