# US 7,411,852 B2 · Semiconductor memory device and method of adjusting same

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- Number: US 7,411,852 B2
- Document ID: US7411852B2
- Status: Granted
- Kind: B2
- Application number: 11/585,948
- Filed: 2006-10-25
- Published: 2007-05-03
- Granted: 2008-08-12
- Earliest claimed: 2005-10-27
- Assignees: Elpida Memory, Inc.
- Inventors: Naohisa Nishioka; Hiroki Fujisawa
- Web page: https://patentgrep.com/patent/US7411852B2

## CPC

- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 17/16: using electrically-fusible links
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A DLL Reset signal for delivering Fuse data from anti-fuses is generated from a reset signal which is supplied asynchronous to a clock when an initial setting is made. The DLL Reset signal is supplied to an anti-fuse block which comprises a plurality of anti-fuses, such that the delay amount of an internal signal is switched to a desired value in accordance with the Fuse data written into the anti-fuses.

## Claims

### Claim 1

A semiconductor memory device comprising:
an anti-fuse block having a plurality of anti-fuses for writing thereinto data required to adjust a timing of an internal signal generated when an initial setting is made;
a delay amount switching circuit for delaying the internal signal by a desired delay amount in accordance with the data;
a latch circuit for generating a command required to read the data from said anti-fuse block based on the internal signal delivered from said delay amount switching circuit after the delay; and
a DLL reset signal generating circuit for supplying said anti-fuse block with a DLL reset signal generated by using the command signal and a reset signal supplied asynchronously to a clock for causing said anti-fuse block to deliver the data.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the DLL reset signal generating circuit is adapted to generate the DLL reset signal based on a PMDCMDT signal supplied from the latch circuit.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the DLL reset signal generating circuit is adapted to receive instructions in accordance with values of a PMRS signal and an ADD2 signal which are code signals.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the DLL reset signal generating circuit is adapted to deliver the DLL reset signal when applied with a reset signal asynchronous to clock CLK, which is supplied from outside during a period of powering on a system generating a MRS CMD signal employed in a DDR3-SDRAM.

### Claim 5

A method of adjusting a semiconductor memory device for adjusting a timing of an internal signal by using data written into anti-fuses when an initial setting is made, said method comprising the steps of:
asynchronously generating a DLL Reset signal for delivering the data from said anti-fuses by using a reset signal supplied asynchronously to a clock; and
supplying the DLL Reset signal to an anti-fuse block including a plurality of anti-fuses which have data written therein required for adjusting the timing of the internal signal.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the DLL reset signal is generated based on a PMDCMDT signal supplied from a latch circuit.

### Claim 7 (depends on 5)

The method according to claim 5, wherein the DLL reset signal is generated using a DLL reset signal generating circuit adapted to generate the DLL reset signal based on a PMDCMDT signal supplied from a latch circuit.

### Claim 8 (depends on 5)

The method according to claim 5, wherein the DLL reset signal is generated using a DLL reset signal generating circuit adapted to deliver the DLL reset signal when applied with a reset signal asynchronous to clock CLK, which is supplied from outside during a period of powering on a system generating a MRS CMD signal employed in a DDR3-SDRAM.

### Claim 9

A method of adjusting a semiconductor device for adjusting the timing of an internal signal by using data written into anti-fuses when an initial setting is made, said method comprising the steps of:
reading data written into the anti-fuses included in said semiconductor device by using a command signal generated within said semiconductor device, and a reset signal supplied asynchronously to a clock signal; and
adjusting the timing of the internal signal in accordance with the data.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the reset signal is generated based on a PMDCMDT signal supplied from a latch circuit.

### Claim 11 (depends on 9)

The method according to claim 9, wherein the reset signal is generated using a DLL reset signal generating circuit adapted to generate the DLL reset signal based on a PMDCMDT signal supplied from a latch circuit.

### Claim 12 (depends on 9)

The method according to claim 9, wherein the reset signal is generated using a DLL reset signal generating circuit adapted to deliver the DLL reset signal when applied with a reset signal asynchronous to clock CLK, which is supplied from outside during a period of powering on a system generating a MRS CMD signal employed in a DDR3-SDRAM.