# US 7,411,831 B2 · Disk processing apparatus with voltage generating circuit having a boost ratio control

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- Number: US 7,411,831 B2
- Document ID: US7411831B2
- Status: Granted
- Kind: B2
- Application number: 11/819,288
- Filed: 2007-06-26
- Published: 2007-10-25
- Granted: 2008-08-12
- Earliest claimed: 2004-04-27
- Assignees: Renesas Technology Corp.
- Inventors: Yoshiki Kawajiri; Masaaki Terasawa; Takanori Yamazoe
- Web page: https://patentgrep.com/patent/US7411831B2

## CPC

- G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)}
- G11C 16/12: Programming voltage switching circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

## Claims

### Claim 1

A data processing circuit comprising:
a control circuit; and
a nonvolatile memory having a voltage generating circuit,
wherein the control circuit is adapted to issue a program instruction to the nonvolatile memory,
wherein, in accordance with the program instruction, the voltage generating circuit generates a program voltage and controls a boosting ratio of the program voltage from a voltage level of an operation voltage to a predetermined voltage level for programming the nonvolatile memory
wherein the boosting ratio is changed from a lower boost ratio in a first period which is an earlier portion of a program voltage generating period, to a higher boost ratio in a second period which is a later portion of the program voltage generating period and in which the program voltage reaches the predetermined voltage level.

### Claim 2 (depends on 1)

A data processing circuit according to claim 1, further comprising a regulator circuit,
wherein the regulator circuit generates the operation voltage for supplying to the control circuit and the nonvolatile memory.

### Claim 3 (depends on 2)

A data processing circuit according to claim 2,
wherein the voltage generating circuit has a clock generating circuit,
wherein the clock generating circuit generates clock signals, one of which is a lower frequency clock signal used in the first period and another of which is a higher frequency clock signal used in the second period.

### Claim 4 (depends on 3)

A data processing circuit according to claim 3,
wherein the nonvolatile memory has a plurality of nonvolatile memory cells, each of which is used for storing data.