# US 7,411,829 B2 · Method and apparatus for programming single-poly pFET-based nonvolatile memory cells

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- Number: US 7,411,829 B2
- Document ID: US7411829B2
- Status: Granted
- Kind: B2
- Application number: 11/528,262
- Filed: 2006-09-26
- Published: 2007-01-25
- Granted: 2008-08-12
- Earliest claimed: 2002-09-16
- Inventors: Christopher J. Diorio; Todd E. Humes
- Web page: https://patentgrep.com/patent/US7411829B2

## CPC

- G11C 16/3468: {Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing}
- G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}
- G11C 16/3472: {Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure}
- G11C 16/3477: {Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection (IHEI). The predetermined event may be, for example, the expiration of a predetermined time period or a determination that a channel has been formed by the BTBT injection process that is sufficiently conducting to support IHEI. Employing BTBT permits a previously overerased or stuck bit to be “unstuck” or “removed” and thus be made usable (i.e., able to be programmed) again.

## Claims

### Claim 1

A method for programming a single-poly pFET-based nonvolatile memory cell, comprising:
providing a single-poly pFET-based non-volatile memory cell having a single-poly pFET including a source, a drain and a floating gate;
applying a reverse-bias voltage across a p-n junction formed between the drain and an n-type semiconductor region within which the drain is formed, said reverse-bias voltage sufficient to generate electrons by band-to-band tunneling (BTBT);
injecting electrons generated by BTBT onto the floating gate;
comparing a source current of said single-poly pFET to a reference current;
upon the source current becoming greater than the reference current, biasing the single-poly pFET to induce impact-ionized hot-electron injection (IHEI); and
injecting electrons generated by IHEI onto the floating gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the single-poly pFET-based nonvolatile memory cell has a stuck bit prior to applying the reverse-bias across the p-n junction.

### Claim 3 (depends on 2)

The method of claim 2, wherein the electrons generated by BTBT and injected onto the floating gate cause the stuck bit to be removed.

### Claim 4 (depends on 1)

The method of claim 1, wherein the single-poly pFET-based nonvolatile memory cell had been previously overerased prior to applying the reverse-bias voltage across the p-n junction.

### Claim 5 (depends on 4)

The method of claim 4, wherein the electrons generated by BTBT and injected onto the floating gate cause the overerased condition to be removed.

### Claim 6

A programming apparatus for programming a single-poly pFET-based nonvolatile memory cell having a single-poly pFET including a drain, a source and a floating gate, said programming apparatus comprising:
a current compare circuit operable to compare a source current flowing through the single-poly pFET to a reference current;
a switch operable to couple either a band-to-band tunneling (BTBT) voltage or an impact-ionized hot-electron injection (IHEI) voltage to the drain of the single-poly pFET; and
a switch control line configured to transmit a switch control signal from said current compare circuit to said switch.

### Claim 7 (depends on 6)

The programming apparatus of claim 6, wherein the switch is configured to couple the BTBT voltage to the drain of the single-poly pFET when the source current is less than the reference current.

### Claim 8 (depends on 6)

The programming apparatus of claim 6, wherein the switch is configured to couple the IHEI voltage to the drain of the single-poly pFET when the source current is greater than the reference current.

### Claim 9 (depends on 6)

The programming apparatus of claim 6, wherein the current compare circuit is further operable to provide a switch control signal to cause said switch to switch from coupling the BTBT voltage to the drain of the single-poly pFET to coupling the IHEI voltage to the drain of the single-poly pFET upon the current compare circuit determining that the source current has exceeded the reference current.

### Claim 10 (depends on 7)

The programming apparatus of claim 7, wherein the single-poly pFET-based nonvolatile memory cell has a stuck bit prior to being programmed by the programming apparatus.

### Claim 11 (depends on 10)

The programming apparatus of claim 10, wherein electrons generated by BTBT and injected onto the floating gate cause the stuck bit to be removed.

### Claim 12 (depends on 7)

The programming apparatus of claim 7, wherein the single-poly pFET-based nonvolatile memory cell had been previously overerased prior to being programmed by the programming apparatus.

### Claim 13 (depends on 12)

The programming apparatus of claim 12, wherein electrons generated by BTBT and injected onto the floating gate cause the overerased condition to be removed.