# US 7,411,828 B2 · Method and apparatus for programming single-poly pFET-based nonvolatile memory cells

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- Number: US 7,411,828 B2
- Document ID: US7411828B2
- Status: Granted
- Kind: B2
- Application number: 11/528,150
- Filed: 2006-09-26
- Published: 2007-01-25
- Granted: 2008-08-12
- Earliest claimed: 2002-09-16
- Inventors: Christopher J. Diorio; Todd E. Humes
- Web page: https://patentgrep.com/patent/US7411828B2

## CPC

- G11C 16/3468: {Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing}
- G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}
- G11C 16/3472: {Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure}
- G11C 16/3477: {Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection (IHEI). The predetermined event may be, for example, the expiration of a predetermined time period or a determination that a channel has been formed by the BTBT injection process that is sufficiently conducting to support IHEI. Employing BTBT permits a previously overerased or stuck bit to be “unstuck” or “removed” and thus be made usable (i.e., able to be programmed) again.

## Claims

### Claim 1

A method for programming a single-poly pFET-based nonvolatile memory cell having a pFET including a drain, a source and a floating gate, said method comprising:
biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
at a second time subsequent to said first time, biasing the pFET to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
at a third time subsequent to said second time, removing the biasing that induced IHEI.

### Claim 3 (depends on 2)

The method of claim 2, wherein said biasing the pFET at a first time includes:
capacitively coupling a relatively high voltage to the floating gate.

### Claim 4 (depends on 3)

The method of claim 3, wherein said biasing the pFET at a first time further includes:
applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 5 (depends on 1)

The method of claim 1, wherein said biasing the pFET at a first time includes:
capacitively coupling a relatively high voltage to the floating gate.

### Claim 6 (depends on 5)

The method of claim 5, wherein said biasing the pFET at a first time further includes:
applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 7

A method for affecting an amount of charge stored on a floating gate of a single-poly pFET having a pFET including a drain, a source and a floating gate, said method comprising:
biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
at a second time subsequent to said first time, biasing the pFET to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
at a third time subsequent to said second time, removing the biasing that induced IHEI.

### Claim 9 (depends on 8)

The method of claim 8, wherein said biasing the pFET at a first time includes:
capacitively coupling a relatively high voltage to the floating gate.

### Claim 10 (depends on 9)

The method of claim 9, wherein said biasing the pFET at a first time further includes:
applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 11 (depends on 7)

The method of claim 7, wherein said biasing the pFET at a first time includes:
capacitively coupling a relatively high voltage to the floating gate.

### Claim 12 (depends on 11)

The method of claim 11, wherein said biasing the pFET at a first time further includes:
applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 13

An apparatus for programming a single-poly pFET-based nonvolatile memory cell having a pFET including a drain, a source and a floating gate, said apparatus comprising:
means for biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
means for biasing the pFET at a second time subsequent to said first time to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.

### Claim 14 (depends on 13)

The apparatus of claim 13, further comprising:
means for removing the biasing that induced IHEI at a third time subsequent to said second time.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein said means for biasing the pFET at a first time includes:
means for capacitively coupling a relatively high voltage to the floating gate.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein said means for biasing the pFET at a first time further includes:
means for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 17 (depends on 13)

The method of claim 13, wherein said means for biasing the pFET at a first time includes:
means for capacitively coupling a relatively high voltage to the floating gate.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein said means for biasing the pFET at a first time further includes:
means for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 19

An apparatus for affecting an amount of charge stored on a floating gate of a single-poly pFET having a drain, a source and a floating gate, said apparatus comprising:
means for biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
means for biasing the pFET at a second time subsequent to said first time to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.

### Claim 20 (depends on 19)

The apparatus of claim 19, further comprising:
means for removing the biasing that induced IHEI at a third time subsequent to said second time.

### Claim 21 (depends on 20)

The apparatus of claim 20, wherein said means for biasing the pFET at a first time includes:
means for capacitively coupling a relatively high voltage to the floating gate.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein said means for biasing the pFET at a first time further includes:
means for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 23 (depends on 19)

The apparatus of claim 19, wherein said means for biasing the pFET at a first time includes:
means for capacitively coupling a relatively high voltage to the floating gate.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein said means for biasing the pFET at a first time further includes:
means for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 25

An apparatus for programming a single-poly pFET-based nonvolatile memory cell having a pFET including a drain, a source and a floating gate, said apparatus comprising:
circuitry for biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
circuitry for biasing the pFET at a second time subsequent to said first time to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.

### Claim 26 (depends on 25)

The apparatus of claim 25, further comprising:
circuitry for removing the biasing that induced IHEI at a third time subsequent to said second time.

### Claim 27 (depends on 26)

The apparatus of claim 26, wherein said circuitry for biasing the pFET at a first time includes:
circuitry for capacitively coupling a relatively high voltage to the floating gate.

### Claim 28 (depends on 27)

The apparatus of claim 27, wherein said circuitry for biasing the pFET at a first time further includes:
circuitry for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 29 (depends on 25)

The apparatus of claim 25, wherein said circuitry for biasing the pFET at a first time includes:
circuitry for capacitively coupling a relatively high voltage to the floating gate.

### Claim 30 (depends on 29)

The apparatus of claim 29, wherein said circuitry for biasing the pFET at a first time further includes:
circuitry for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 31

An apparatus for affecting an amount of charge stored on a floating gate of a single-poly pFET having a drain, a source and a floating gate, said apparatus comprising:
circuitry for biasing the pFET at a first time to induce band-to-band tunneling (BTBT) and thereby inject electrons onto the floating gate; and
circuitry for biasing the pFET at a second time subsequent to said first time to induce impact-ionized hot-electron injection (IHEI) and thereby inject electrons onto the floating gate.

### Claim 32 (depends on 31)

The apparatus of claim 31, further comprising:
circuitry for removing the biasing that induced IHEI at a third time subsequent to said second time.

### Claim 33 (depends on 32)

The apparatus of claim 32, wherein said circuitry for biasing the pFET at a first time includes:
circuitry for capacitively coupling a relatively high voltage to the floating gate.

### Claim 34 (depends on 33)

The apparatus of claim 33, wherein said circuitry for biasing the pFET at a first time further includes:
circuitry for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.

### Claim 35 (depends on 31)

The apparatus of claim 31, wherein said circuitry for biasing the pFET at a first time includes:
circuitry for capacitively coupling a relatively high voltage to the floating gate.

### Claim 36 (depends on 35)

The apparatus of claim 35, wherein said circuitry for biasing the pFET at a first time further includes:
circuitry for applying a relatively low voltage to the drain of the pFET simultaneously with said capacitive coupling.