# US 7,411,822 B2 · Nonvolatile memory cell arrangement > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,822 B2 - Document ID: US7411822B2 - Status: Granted - Kind: B2 - Application number: 11/283,572 - Filed: 2005-11-18 - Published: 2006-08-17 - Granted: 2008-08-12 - Earliest claimed: 2004-11-19 - Assignees: Infineon Technologies AG - Inventors: Michael Specht; Franz Hofmann; Ulrich Dorda; Johannes Kretz; Lars Dreeskornfeld - Web page: https://patentgrep.com/patent/US7411822B2 ## CPC - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/30: characterised by the memory core region - H10D 30/0411: {of FETs having floating gates} - H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} - H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)} - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures} - H10D 64/037: {comprising charge-trapping insulators} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/62: Fin field-effect transistors [FinFET] - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane. ## Claims ### Claim 1 A memory, comprising: a multiplicity of nonvolatile memory cells, each nonvolatile memory cell being formed by a memory transistor configured so that electrical charge carriers are stored in nonvolatile fashion; the memory transistors are arranged in a matrix having a plurality of rows and columns; a first source/drain terminal of each memory transistor of a first column coupled to an electrically conductive conductor track in a first metallization plane; a first source/drain terminal of each memory transistor of a second column adjacent to the first column coupled to an electrically conductive conductor track in a second metallization plane; a first source/drain terminal of each memory transistor of a third column adjacent to the second column coupled to an electrically conductive conductor track in the first metallization plane; and a first source/drain terminal of each memory transistor of a fourth column adjacent to the third column coupled to an electrically conductive conductor track in the second metallization plane, wherein the second metallization plane is different than the first metallization plane, wherein a second source/drain terminal of each memory transistor is connected to a respective electrically conductive conductor track in a third metallization plane, the third metallization plane being different than the first metallization plane and different than the second metallization plane. ### Claim 2 (depends on 1) The memory of claim 1, wherein the memory transistors are coupled to one another in a NOR circuit. ### Claim 3 (depends on 1) The memory of claim 1, wherein the memory transistors each have an ONO charge storage layer in which the electrical charge carriers can be stored in nonvolatile fashion. ### Claim 4 (depends on 1) The memory of claim 1, wherein the memory transistors each have a floating gate charge storage layer in which the electrical charge carriers can be stored in nonvolatile fashion. ### Claim 5 (depends on 1) The memory of claim 1, wherein the memory transistors are silicon memory transistors. ### Claim 6 (depends on 1) The memory of claim 1, wherein at least one portion of the memory transistors is formed in a 6F2 basic area or in a 4F2 basic area. ### Claim 7 (depends on 1) The memory of claim 1, wherein the second metallization plane is arranged above the first metallization plane. ### Claim 8 (depends on 7) The memory of claim 7, wherein the second metallization plane is the metallization plane arranged directly above the first metallization plane. ### Claim 9 (depends on 1) The memory of claim 1, wherein the third metallization plane is arranged above the second metallization plane. ### Claim 10 (depends on 9) The memory of claim 9, wherein the third metallization plane is the metallization plane arranged directly above the second metallization plane. ### Claim 11 (depends on 1) The memory of claim 1, wherein the fourth metallization plane is arranged above the third metallization plane. ### Claim 12 (depends on 11) The memory of claim 11, wherein the fourth metallization plane is the metallization plane arranged directly above the third metallization plane. ### Claim 13 (depends on 1) The memory of claim 1, wherein the first metallization plane is a metallization plane 1 of the nonvolatile memory cell arrangement, and the second metallization plane is a metallization plane 2 of the nonvolatile memory cell arrangement. ### Claim 14 (depends on 1) The memory of claim 1, wherein the third metallization plane is a metallization plane 3 of the nonvolatile memory cell arrangement. ### Claim 15 (depends on 1) The memory of claim 1, wherein the fourth metallization plane is a metallization plane 4 of the nonvolatile memory cell arrangement. ### Claim 16 (depends on 1) The memory of claim 1, wherein the memory transistors are fin field effect transistors. ### Claim 17 (depends on 16) The memory of claim 16, the memory transistors are bulk fin field effect transistors. ### Claim 18 A nonvolatile memory cell arrangement, comprising: a multiplicity of nonvolatile memory cells, each nonvolatile memory cell being formed by a memory transistor configured so that electrical charge carriers are stored in nonvolatile fashion, and wherein the memory transistors are arranged in a matrix having a plurality of rows and columns; a first source/drain terminal of each memory transistor of a first column coupled to an electrically conductive conductor track in a first metallization plane; a first source/drain terminal of each memory transistor of a second column adjacent to the first column coupled to an electrically conductive conductor track in a second metallization plane; a first source/drain terminal of each memory transistor of a third column adjacent to the second column coupled to an electrically conductive conductor track in the first metallization plane; and a first source/drain terminal of each memory transistor of a fourth column adjacent to the third column coupled to an electrically conductive conductor track in the second metallization plane, wherein the first and second metallization planes are not the same, wherein the conductor tracks are arranged in the column direction alongside the source/drain terminals and have, alongside a portion of the source/drain terminals of the memory transistors of a column, a projection extending perpendicularly to the column direction as far as above the respective source/drain terminal, and wherein the conductor tracks are coupled to the respective source/drain terminal by means of a respective projection and by means of a contact hole respectively provided below the latter. ### Claim 19 A memory comprising: a plurality of memory cell transistors arranged in a matrix having a plurality of rows and columns; a first source/drain terminal of each memory transistor of a first column coupled to an electrically conductive conductor track in a first metallization plane; a first source/drain terminal of each memory transistor of a second column adjacent to the first column coupled to an electrically conductive conductor track in a second metallization plane; a first source/drain terminal of each memory transistor of a third column adjacent to the second column coupled to an electrically conductive conductor track in the first metallization plane; and a first source/drain terminal of each memory transistor of a fourth column adjacent to the third column coupled to an electrically conductive conductor track in the second metallization plane, the second metallization plane being different than the first metallization plane, wherein second source/drain terminal of each memory transistor is connected to a respective electrically conductive conductor track in a third metallization plane, the third metallization plane being different than the first metallization plane and different than the second metallization plane.