# US 7,411,815 B2 · Memory write circuit

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- Number: US 7,411,815 B2
- Document ID: US7411815B2
- Status: Granted
- Kind: B2
- Application number: 11/273,248
- Filed: 2005-11-14
- Published: 2007-05-17
- Granted: 2008-08-12
- Earliest claimed: 2005-11-14
- Assignees: Infineon Technologies AG; Altis Semiconductor
- Inventors: Dietmar Gogl
- Web page: https://patentgrep.com/patent/US7411815B2

## CPC

- G11C 7/02: with means for avoiding parasitic signals
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A design for a memory array that uses bi-directional write currents and that avoids switched ground connections for memory cells, thereby reducing signal loss and noise problems is described. Positive and negative current sources are provided to supply the bi-directional current that is used to write to a memory cell. These current sources may be selectively connected to bit lines that are electrically connected to the memory cells. Applying a positive current, from the positive current source, through a memory cell writes a “1”, and applying a negative current, from the negative current source, through a memory cell writes a “0”. Use of both a positive and a negative current source enables writing to the memory cells without relying on a switched ground connection to provide bi-directional current. This permits a ground connection of each memory cell to be connected to a fixed ground. An example in which this design is used with a spin injection magneto-resistive random access memory (MRAM) device is shown.

## Claims

### Claim 1

A memory device comprising:
a plurality of word lines;
a plurality of bit lines; and
a plurality of memory cells, each memory cell in the plurality of memory cells having a first connection coupled to one of the bitlines, a second connection coupled to one of the word lines and a ground connection;
wherein each memory cell is electrically connected such that current is capable of flowing through the memory cell between the first connection and the ground connection in a positive direction and in a negative direction;
wherein each memory cell in the plurality of memory cells is configured so that a first logical value is written to the memory cell by application of a current in the positive direction through the memory cell, and a second logical value is written to the memory cell by application of a current in the negative direction through the memory cell; and
wherein the ground connection of each memory cell in the plurality of memory cells is electrically connected to a fixed ground.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the fixed ground comprises a low resistive ground connection.

### Claim 3 (depends on 1)

The memory device of claim 1, further comprising a positive current source and a negative current source, wherein each of the positive current source and the negative current source are selectively electrically connected to the first connection of a particular memory cell in the plurality of memory cells such that:
when the positive current source is electrically connected to the first connection of the particular memory cell, current flows through the particular memory cell in the positive direction, thereby writing the first logical value to the particular memory cell; and
when the negative current source is electrically connected to the first connection of the particular memory cell, current flows through the particular memory cell in the second direction, thereby writing the second logical value to the particular memory cell.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the negative current source comprises a charge pump circuit.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the positive current source is derived from a supply voltage of a chip on which the plurality of memory cells are located.

### Claim 6 (depends on 3)

The memory device of claim 3, wherein the positive current source comprises a charge pump circuit.

### Claim 7 (depends on 3)

The memory device of claim 3, wherein the positive current source and the negative current source are selectively electrically connected to the first connection of the particular memory cell through a particular one of the bit lines.

### Claim 8 (depends on 7)

The memory device of claim 7, further comprising a column selector circuit coupled between the positive current source and the bit lines and between the negative current source and the bit lines.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein each memory cell in the plurality of memory cells comprises a select transistor having a gate such that current is prevented from flowing through the memory cell when the gate is deactivated.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the gate is activated by application of an activation voltage, and is deactivated when the gate is coupled to ground.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the gate of the select transistor of each memory cell in the plurality of memory cells is electrically connected to one of the word lines.

### Claim 12 (depends on 11)

The memory device of claim 11, further comprising a row decoder circuit that selectively applies the activation voltage to a particular one of the word lines and connects all other word lines to ground.

### Claim 13 (depends on 1)

The memory device of claim 1, wherein the memory device comprises a spin-injection magneto-resistive random access memory device, and wherein each memory cell in the plurality of memory cells comprises a magnetic tunnel junction.

### Claim 14 (depends on 1)

The memory device of claim 1, wherein the memory device comprises a conductive bridging random access memory device.

### Claim 15

A memory cell comprising:
a first connection and a ground connection, wherein current is capable of flowing through the memory cell between the first connection and the ground connection in a positive and a negative direction, wherein the ground connection of the memory cell is electrically connected to a fixed ground; and
a junction element, wherein applying a current through the junction element in the positive direction writes a first logical value to the memory cell and applying current through the junction element in the negative direction writes a second logical value to the memory cell.

### Claim 16 (depends on 15)

The memory cell of claim 15, wherein the fixed ground comprises a low resistive ground connection.

### Claim 17 (depends on 15)

The memory cell of claim 15, further comprising a select transistor coupled in series to the junction element, wherein the select transistor prevents current from flowing through the junction element when the select transistor is deactivated.

### Claim 18 (depends on 17)

The memory cell of claim 17, wherein the select transistor is activated by application of an activation voltage to a gate of the select transistor.

### Claim 19 (depends on 15)

The memory cell of claim 15, wherein the memory cell comprises a spin-injection magneto-resistive random access memory cell, and wherein the junction element comprises a magnetic tunnel junction.

### Claim 20 (depends on 15)

The memory cell of claim 15, wherein the memory cell comprises a conductive bridging random access memory device (CBRAM), and wherein the junction element comprises a CBRAM junction.

### Claim 21

A method of operating a memory device, the method comprising:
providing a memory cell that includes a first connection and a ground connection;
flowing a current through the memory cell between the first connection and the ground connection, wherein the memory cell is electrically connected such that the current is capable of flowing through the memory cell in a positive direction and in a negative direction and wherein a first logical value or a second logical value is written to the memory cell depending on whether the current is a positive or a negative current through the memory cell; and
electrically connecting the ground connection of the memory cell to a fixed ground.

### Claim 22 (depends on 21)

The method of claim 21, wherein flowing a current through the memory cell comprises providing a positive current source that derives the positive current from a supply voltage of the memory device.

### Claim 23 (depends on 21)

The method of claim 21, wherein the memory device comprises a magneto-resistive random access memory device and the memory cell comprises a magnetic tunnel junction, wherein the method further comprises:
applying the positive current through the magnetic tunnel junction to write the first logical value to the memory cell; and
applying the negative current through the magnetic tunnel junction to write the second logical value to the memory cell.