# US 7,411,810 B2 · One-time programmable memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,810 B2 - Document ID: US7411810B2 - Status: Granted - Kind: B2 - Application number: 11/669,156 - Filed: 2007-01-30 - Published: 2007-06-14 - Granted: 2008-08-12 - Earliest claimed: 2007-01-30 - Inventors: Juhan Kim - Web page: https://patentgrep.com/patent/US7411810B2 ## CPC - G11C 11/24: using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) - G11C 8/10: Decoders - G11C 17/16: using electrically-fusible links - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - H10D 88/00: Three-dimensional [3D] integrated devices - H10B 20/00: Read-only memory [ROM] devices - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal is floating, and the fourth terminal is connected to a bit line, and the capacitor includes two electrodes, wherein one of the capacitor plate serves as a storage node which is connected to the second terminal of the diode, and another plate of the capacitor is connected to a plate line, and the plate line is asserted to programming voltage which is higher than the regular supply voltage of the decoders and data latches, in order to breakdown the insulator of the capacitor when programming, but the plate line is connected to the regular supply voltage when read. And during read, the diode also serves as a sense amplifier to detect whether the storage node is forward bias or not, and it sends binary data to a latch device wherein includes a current mirror and a feedback loop, which cuts off the current path after latching. And dummy columns generate replica delay signals which guarantee timing margin and reduce cycle time. In addition, the memory cells are formed in between the routing layers, which memory cells can be stacked over the transistor or another capacitor memory cell. ## Claims ### Claim 1 A memory device, comprising: memory cell, wherein includes a diode as an access device and a capacitor as a storage device; and the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal is floating, and the fourth terminal is connected to a bit line; and the capacitor includes two plates, wherein one plate of the capacitor serves as a storage node which is connected to the second terminal of the diode, and another plate of the capacitor is connected to a plate line; and the plate line is asserted to programming voltage which is higher than the regular supply voltage of the decoders and data latches, in order to breakdown the insulator of the capacitor when programming, but the plate line is connected to the regular supply voltage when read; memory cell array, wherein includes decoders, data latches, main memory cells and dummy memory cells; and main memory cells configure main columns, dummy memory cells configure dummy column(s), dummy column(s) generates delayed signal based on the dummy cells to enable the main columns in order to start latching the stored data from the memory cell; and data latch, wherein includes current mirror and latch circuit, the current mirror is connected to the diode through the bit line, and the latch circuit is connected to the current mirror, and the latch circuit cuts off the current path of the bit line after latching data from the memory cell, when read. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the diode includes four terminals, the first terminal is p-type, the second terminal is n-type, the third terminal is p-type, and the fourth terminal is n-type. ### Claim 3 (depends on 1) The memory device of claim 1, wherein at least one terminal of the diode includes metal to form Schottky diode. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the diode is formed from silicon including polysilicon, amorphous silicon, and stretchable silicon. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the diode is formed from germanium. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the diode is formed from compound semiconductor. ### Claim 7 (depends on 1) The memory device of claim 1, wherein at least one terminal of the diode is vertically formed on the other terminal of the diode. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the memory cells are formed (stacked over) on the MOS transistor. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the memory cells are formed on the bulk wafer. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the memory cells are formed on the SOI wafer. ### Claim 11 (depends on 1) The memory device of claim 1, wherein two memory cells are stacked on the wafer. ### Claim 12 (depends on 1) The memory device of claim 1, wherein the current mirror in the data latch includes lower threshold NMOS transistor than that of control circuit in the chip. ### Claim 13 (depends on 1) The memory device of claim 1, wherein the memory cell is implemented an alternative embodiment with reverse configuration; and the diode, wherein includes four terminals, the first terminal is n-type and serves as a word line, the second terminal is p-type and serves as a storage node, the third terminal is n-type and floating, and the fourth terminal is p-type and serves as a bit line; and the plate line is asserted to lower voltage than ground level, when programmed; and data latch, wherein includes current mirror and latch circuit, the current mirror is connected to the diode through the bit line, and the latch circuit is connected to the current mirror, and the latch circuit cuts off the current path of the bit line after latching data from the memory cell, when read. ### Claim 14 (depends on 13) The memory device of claim 13, wherein the current mirror in the data latch includes lower threshold PMOS transistor than that of control circuit in the chip.