# US 7,411,809 B2 · Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same

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- Number: US 7,411,809 B2
- Document ID: US7411809B2
- Status: Granted
- Kind: B2
- Application number: 11/417,154
- Filed: 2006-05-04
- Published: 2007-05-17
- Granted: 2008-08-12
- Earliest claimed: 2005-11-17
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Ryu Ogiwara; Daisaburo Takashima
- Web page: https://patentgrep.com/patent/US7411809B2

## CPC

- G11C 11/22: using ferroelectric elements
- G11C 29/06: Acceleration testing
- G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C 29/12005: {comprising voltage or current generators}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 2029/1204: {Bit line control}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A unit cell is formed by a ferroelectric capacitor and first MOS transistor, and a block is formed by connecting a plurality of unit cells in series. The gates of the first MOS transistors in the individual unit cells are connected to word lines, which are selectively driven by a word line driver on the basis of a row address signal. A plate line is connected to one terminal of the block, and driven by a plate line driver. A bit line is connected to the other terminal of the block via a second MOS transistor for block selection, and selected by a column decoder on the basis of a column address. A driver/controller controls the plate line driver and column decoder to apply a potential difference between the plate line and bit line, while a plurality of word lines are kept off.

## Claims

### Claim 1

A ferroelectric memory comprising:
a block in which a plurality of unit cells each formed by connecting two electrodes of a ferroelectric capacitor to a source and drain of a first MOS transistor are connected in series;
word lines each connected to a gate of the first MOS transistor;
a word line driver which selectively drives the word lines on the basis of a row address signal;
a plate line connected to one terminal of the block;
a plate line driver which drives the plate line;
a bit line connected to the other terminal of the block via a second MOS transistor for block selection;
a column decoder which selects the bit line on the basis of a column address signal; and
a driver/controller configured to apply a potential difference between the plate line and the bit line while said plurality of word lines are kept off, the driver/controller generating and outputting a driving signal for the plate line by receiving a driving potential in a normal mode of the plate line and a testing plate line potential from the plate line driver, and generating and outputting a driving signal for the bit line by receiving a testing bit line potential from the column decoder.

### Claim 2

A ferroelectric memory comprising:
a block in which a plurality of unit cells each formed by connecting two electrodes of a ferroelectric capacitor to a source and drain of a first MOS transistor are connected in series;
word lines each connected to a gate of the first MOS transistor;
a word line driver which selectively drives the word lines on the basis of a row address signal;
a plate line connected to one terminal of the block;
a plate line driver which drives the plate line;
a bit line connected to the other terminal of the block via a second MOS transistor for block selection;
a column decoder which selects the bit line on the basis of a column address signal; and
a driver/controller configured to apply a potential difference between the plate line and the bit line while said plurality of word lines are kept off, wherein the driver/controller simultaneously applies a potential difference in a direction to weaken polarization to a plurality of unit cells in a block placed between the plate line and the bit line.

### Claim 3 (depends on 1)

A memory according to claim 1, wherein the driver/controller comprises a first circuit which supplies a potential to the plate line, and a second circuit which supplies a potential to the bit line.

### Claim 4 (depends on 3)

A memory according to claim 3, wherein the first circuit comprises a third MOS transistor of a first-conductivity-type which has a current path one end of which is supplied with a plate line driving potential in a normal mode, a first NAND gate which is supplied with a row address signal, a plate line enable signal, and a signal for designating one of the normal mode and a test mode, a first inverter which is supplied with an output signal from the first NAND gate, a second inverter which is supplied with an output signal from the first inverter and supplies an output signal to a gate of the third MOS transistor, a fourth MOS transistor of the first-conductivity-type which has a current path one end of which is supplied with a testing plate line potential, and the other end of the current path connected to the other end of the current path of the third MOS transistor, a second NAND gate which is supplied with the row address signal and a plate line test signal, a third inverter which is supplied with an output signal from the second NAND gate, a fourth inverter which is supplied with an output signal from a third inverter and supplies an output signal to a gate of the fourth MOS transistor, a fifth MOS transistor of a second-conductivity-type which has a current path one end of which is connected to the other ends of the third MOS transistor and the fourth MOS transistor, and the other end of the current path connected to a ground point, a third NAND gate which is supplied with the plate line enable signal and the signal for designating one of the normal mode and the test mode, a fourth NAND gate which is supplied with an output signal from the third NAND gate and an inverted signal of the plate line test signal, and a fifth NAND gate which is supplied with an output signal from the fourth NAND gate and the row address signal and supplies an output signal to a gate of the fifth MOS transistor, and outputs a signal for driving the plate line from a connecting point of the current paths of the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor.

### Claim 5 (depends on 4)

A memory according to claim 4, wherein the second circuit comprises a sixth MOS transistor of the second-conductivity-type which has a current path one end of which is applied to a testing bit line potential, a sixth NAND gate which is supplied with a column address signal, a bit line equalizing signal, and a bit line test signal, a fifth inverter which is supplied with an output signal from the sixth NAND gate and supplies an output signal to a gate of the sixth MOS transistor, a seventh MOS transistor of the second-conductivity-type which has a current path one end of which is connected to the other end of the current path of the sixth MOS transistor, and the other end of the current path connected to a ground point, a NOR gate which is supplied with an inverted signal of the bit line equalizing signal and an inverted signal of the bit line test signal, and a seventh NAND gate which is supplied with an output signal from the NOR gate and the column address signal and supplies an output signal to a gate of the seventh MOS transistor, and outputs a signal for driving the bit line from a connecting point of the current paths of the sixth MOS transistor and the seventh MOS transistor.

### Claim 6 (depends on 1)

A memory according to claim 1, wherein the word lines and the plate line run parallel to each other, and the bit line runs in a direction to intersect the word lines and the plate line.

### Claim 7 (depends on 6)

A memory according to claim 6, further comprising a sense amplifier which amplifies a potential of the bit line.

### Claim 8 (depends on 7)

A memory according to claim 7, further comprising a signal line which externally applies a bit line driving potential in a normal mode to the bit line, and a transfer gate which is inserted between the signal line and the bit line, and transfers the bit line driving potential from the signal line to the bit line.

### Claim 9 (depends on 8)

A memory according to claim 8, further comprising a DQ line running in a direction to intersect the bit line, and a DQ sense amplifier which amplifies a potential of the DQ line.

### Claim 10 (depends on 2)

A memory according to claim 2, wherein the driver/controller comprises a first circuit which supplies a potential to the plate line, and a second circuit which supplies a potential to the bit line.

### Claim 11 (depends on 10)

A memory according to claim 10, wherein the first circuit comprises a third MOS transistor of a first conductivity type which has a current path one end of which is supplied with a plate line driving potential in a normal mode, a first NAND gate which is supplied with a row address signal, a plate line enable signal, and a signal for designating one of the normal mode and a test mode, a first inverter which is supplied with an output signal from the first NAND gate, a second inverter which is supplied with an output signal from the first inverter and supplies an output signal to a gate of the third MOS transistor, a fourth MOS transistor of the first-conductivity-type which has a current path one end of which is supplied with a testing plate line potential, and the other end of the current path connected to the other end of the current path of the third MOS transistor, a second NAND gate which is supplied with the row address signal and a plate line test signal, a third inverter which is supplied with an output signal from the second NAND gate, a fourth inverter which is supplied with an output signal from a third inverter and supplies an output signal to a gate of the fourth MOS transistor, a fifth MOS transistor of a second conductivity type which has a current path one end of which is connected to the other ends of the third MOS transistor and the fourth MOS transistor, and the other end of the current path connected to a ground point, a third NAND gate which is supplied with the plate line enable signal and the signal for designating one of the normal mode and the test mode, a fourth NAND gate which is supplied with an output signal from the third NAND gate and an inverted signal of the plate line test signal, and a fifth NAND gate which is supplied with an output signal from the fourth NAND gate and the row address signal and supplies an output signal to a gate of the fifth MOS transistor, and outputs a signal for driving the plate line from a connecting point of the current paths of the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor.

### Claim 12 (depends on 11)

A memory according to claim 11, wherein the second circuit comprises a sixth MOS transistor of the second-conductivity-type which has a current path one end of which is applied to a testing bit line potential, a sixth NAND gate which is supplied with a column address signal, a bit line equalizing signal, and a bit line test signal, a fifth inverter which is supplied with an output signal from the sixth NAND gate and supplies an output signal to a gate of the sixth MOS transistor, a seventh MOS transistor of the second conductivity type which has a current path one end of which is connected to the other end of the current path of the sixth MOS transistor, and the other end of the current path connected to a ground point, a NOR gate which is supplied with an inverted signal of the bit line equalizing signal and an inverted signal of the bit line test signal, and a seventh NAND gate which is supplied with an output signal from the NOR gate and the column address signal and supplies an output signal to a gate of the seventh MOS transistor, and outputs a signal for driving the bit line from a connecting point of the current paths of the sixth MOS transistor and the seventh MOS transistor.

### Claim 13 (depends on 2)

A memory according to claim 2, wherein the word lines and the plate line run parallel to each other, and the bit line runs in a direction to intersect the word lines and the plate line.

### Claim 14 (depends on 13)

A memory according to claim 13, further comprising a sense amplifier which amplifies a potential of the bit line.

### Claim 15 (depends on 14)

A memory according to claim 14, further comprising a signal line which externally applies a bit line driving potential in a normal mode to the bit line, and a transfer gate which is inserted between the signal line and the bit line, and transfers the bit line driving potential from the signal line to the bit line.

### Claim 16 (depends on 15)

A memory according to claim 15, further comprising a DQ line running in a direction to intersect the bit line, and a DQ sense amplifier which amplifies a potential of the DQ line.