# US 7,411,530 B2 · Method for the evaluation of a first analog signal and a second analog signal, and evaluation circuit corresponding therewith > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,530 B2 - Document ID: US7411530B2 - Status: Granted - Kind: B2 - Application number: 11/632,524 - Filed: 2005-07-07 - Published: 2007-10-18 - Granted: 2008-08-12 - Earliest claimed: 2004-07-14 - Assignees: Siemens Aktiengesellschaft - Inventors: Hans-Georg Köpken - Web page: https://patentgrep.com/patent/US7411530B2 ## CPC - G01D 5/24495: {using previous values} - G01D 5/2448: {Correction of gain, threshold, offset or phase control} - H03M 1/06: Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) - H03M 1/303: {Circuits or methods for processing the quadrature signals} - G01D: MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Two analog signals are substantially sinusoidal and out-of-phase by about 9020 relative to each other when an element moves in a temporally uniform manner in relation to a stationary element. The two analog signals make it possible to determine the actual position of the moving element relative to the stationary element. The analog signals have a corresponding maximum frequency when the moving element moves at a maximum speed. The signals are detected by sensor units and are fed to AD converters which digitize the signals at a scanning frequency and feed corresponding digital signals to an evaluation block that is configured as a hardware circuit, the scanning frequency of the AD converters being more than twice as large as the maximum frequency. The digital signals are fed to a computing block within the evaluation block, said computing block calculating an arc tangent that corresponds to the digital signals in real time. The evaluation block also determines corrective values for the digital signals in real time based on the digital signals. ## Claims ### Claim 1 A method for an evaluation of a first analog signal and a second analog signal, comprising: providing the analog signals substantially sinusoidal and out of phase by about 90° relative to each other when an element moves in a temporally uniform manner relative to a stationary element; recording the first analog signal by first sensor unit; recording the second analog signal by second sensor unit; sending the first analog signal and the second analog signal unit to an AD converter; digitalizing the analog signals by the AD converters at a scanning frequency, wherein the scanning frequency of the AD converters is more than twice as large as a maximum frequency; sending a corresponding digital signal to an evaluation block that is configured as a hardware circuit; determining an arc tangent corresponding to the digital signals in real time by the evaluation block; determining correction values for the first and second signal corresponding to the digital signals in real time by the evaluation block; sending the digital signals to a computing block within the evaluation block; and calculating the arc tangent in real time, wherein a correction-value add-on block that is configured as a hardware circuit is arranged between the AD converters and the evaluation block, the evaluation block feeds the correction values to the correction-value add-on block and the correction-value add-on block corrects the digital signals by the correction values and outputs the corrected digital signals to the evaluation block. ### Claim 2 (depends on 1) The evaluation method as claimed in claim 1, wherein the computing block calculates from the digital signals fed to it a corresponding vector length, the computing block feeds the arc tangent and the vector length to a correction-value determining block that is configured as a hardware circuit, the correction-value determining block has a number of registers to which an angular range is respectively assigned, the correction-value determining block selects based upon the arc tangent the particular register in whose angular range the arc tangent lies, the correction-value determining block stores the vector length in the selected register, and the correction-value determining block updates the correction values based upon the vector lengths stored in the registers. ### Claim 3 (depends on 2) The evaluation method as claimed in claim 2, wherein the correction-value determining block sets a flag assigned to the selected register each time a vector length is stored, the correction-value determining block updates the correction values only when all the flags are set, and the correction-value determining block, in connection with the updating of the correction values, resets all the flags. ### Claim 4 (depends on 2) The evaluation method as claimed in claim 2, wherein the correction-value determining block stores the correction values in internal memories, to update the correction values, the correction-value determining block first calculates based upon the vector lengths stored in the registers correction-value change values in a change-value determining circuit and the correction-value determining block adds the correction-value change values in accumulators to the correction values and stores them as new correction values. ### Claim 5 (depends on 4) The evaluation method as claimed in claim 4, wherein the correction-value determining block first calculates in summators and differentiators by summation and differentiation basic correction values based upon the vector lengths stored in the registers, the correction-value determining block multiplies the basic correction values in multipliers with weighting factors and the correction-value change values correspond to the basic correction values multiplied with the weighting factors. ### Claim 6 (depends on 2) The evaluation method as claimed in claim 2, wherein the angular ranges of the registers cover in their entirety less than 360°, wherein the correction-value determining block updates the correction values based upon the angular ranges of the registers. ### Claim 7 (depends on 1) The evaluation method as claimed in claim 1, wherein the scanning frequency is at least four times as large as the maximum frequency or least sixteen times as large as the maximum frequency. ### Claim 8 (depends on 1) The evaluation method as claimed in claim 1, wherein the correction values for the first and the second signal comprise two offset correction values, at least one amplitude correction value and at least one phase correction value. ### Claim 9 (depends on 1) The evaluation method as claimed in claim 1, wherein a clock signal with a clock frequency is fed to a synchronization circuit, the synchronization circuit readjusts the scanning frequency based upon the clock frequency such that the scanning frequency is an integral multiple of the clock frequency, and the synchronization circuit feeds the scanning frequency to the AD converters and the evaluation block. ### Claim 10 (depends on 9) The evaluation method as claimed in claim 9, wherein the synchronization circuit outputs on the basis of a slope of the clock signal a trigger signal to the evaluation block and in that the evaluation block determines and outputs the actual position of the moving element when the trigger signal is applied. ### Claim 11 (depends on 10) The evaluation method as claimed in claim 10, wherein the evaluation block averages a plurality of positions of the moving element determined based upon the arc tangent and in that the average value corresponds to the actual position. ### Claim 12 (depends on 11) The evaluation method as claimed in claim 11, wherein the evaluation block monitors the arc tangent for an angular jump and determining the actual position based upon the angular jump. ### Claim 13 (depends on 1) The evaluation method as claimed in claim 1, wherein the analog signals are low-pass filtered before digitizing with a limiting frequency and in that the limiting frequency lies between the maximum frequency and the scanning frequency. ### Claim 14 An evaluation circuit for a first analog signal and a second analog signal, comprising: analog signals substantially sinusoidal and out of phase by about 90° relative to each other when an element moves in a temporally uniform manner relative to a stationary element, the first analog signal or the second analog signal are send to at least two AD converters; the AD converters digitize the analog signals that are send to them at a scanning frequency, wherein the scanning frequency of the AD converters is more than twice as large as a maximum frequency, to output digital signals of the AD converters correspond to the received analog signals; an evaluation block configured as a hardware circuit, calculates the arc tangent in real time and includes a computing block to which the digital signals are send; a connection between the AD converters and the evaluation block to send the digital signals from the output of the AD converters to the evaluation block, wherein the evaluation block is configured such that it determines from the digital signals fed to it in real time an arc tangent corresponding to the digital signals and correction values for the first and the second signal; and a correction-value add-on block that is configured as a hardware circuit is arranged between the AD converters and the evaluation block; wherein the correction values are send to the correction-value add-on block by the evaluation block and the digital signals by the AD converters, and wherein the correction-value add-on block corrects the digital signals by the correction values and the correction-value add-on block outputs the corrected digital signals to the evaluation block. ### Claim 15 (depends on 14) The evaluation method as claimed in claim 14, wherein a clock signal with a clock frequency is fed to a synchronization circuit, the synchronization circuit readjusts the scanning frequency based upon the clock frequency such that the scanning frequency is an integral multiple of the clock frequency, and the synchronization circuit feeds the scanning frequency to the AD converters and the evaluation block. ### Claim 16 (depends on 14) The evaluation circuit as claimed in claims 14, wherein low-pass filters are connected upstream of the AD converters, the low-pass filters having a limiting frequency between the maximum frequency and the scanning frequency. ### Claim 17 (depends on 14) The evaluation circuit as claimed in claim 14, wherein the computing block is configured as a CORDIC block. ### Claim 18 (depends on 14) The evaluation circuit as claimed in claim 14, wherein the evaluation block is configured as an application-specific integrated circuit.