# US 7,411,453 B1 · Tail-current steering circuit and method for rail-to-rail operational amplifier input stage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,453 B1 - Document ID: US7411453B1 - Status: Granted - Kind: B1 - Application number: 11/655,524 - Filed: 2007-01-19 - Published: 2008-07-24 - Granted: 2008-08-12 - Earliest claimed: 2007-01-19 - Assignees: Texas Instruments Incorporated - Inventors: Vadim V. Ivanov; David R. W. Spady - Web page: https://patentgrep.com/patent/US7411453B1 ## CPC - H03F 3/45192: {Folded cascode stages} - H03F 3/4565: {Controlling the common source circuit of the differential amplifier} - H03F 2200/456: A scaled replica of a transistor being present in an amplifier - H03F 2203/45466: the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit - H03F 2203/45476: the CSC comprising a mirror circuit - H03F: AMPLIFIERS ## Abstract An amplifier includes first and second pairs of differentially coupled input transistors. The first current mirror generates a reference current which is mirrored by a second current mirror to produce a mirrored reference current. Current steering circuitry steers the mirrored reference current as a first tail current through the first pair when a common mode voltage associated with a differential input voltage exceeds a first reference voltage. A first portion of the mirrored reference current flows from the first current steering circuitry when the common mode voltage is greater than the first reference voltage to produce a second tail current for the second pair. A second portion of the mirrored reference current is fed back to an output of the first current mirror and summed with the reference current so as to reduce the second portion when the common mode voltage is greater than the first reference voltage. ## Claims ### Claim 1 Amplifier circuitry comprising: (a) first and second pairs of differentially coupled input transistors, each transistor having a first electrode, a second electrode, and a control electrode, a differential input voltage being coupled between the control electrodes of the first pair and also being coupled between the control electrodes of the second pair, the second electrodes of the first and second pairs of differentially coupled input transistors being coupled to a folded cascode stage; (b) first current mirror circuitry for generating a reference current; (c) second current mirror circuitry receiving the reference current and producing a mirrored reference current; (d) current steering circuitry operative to steer the mirrored reference current as a first tail current through the first electrodes of the transistors of the first pair when a common mode input voltage of the amplifier circuitry exceeds a first reference voltage; (e) third current mirror circuitry receiving and amplifying a first portion of the mirrored reference current from the current steering circuitry when the common mode voltage is less than the first reference voltage to produce a second tail current through the first electrodes of the transistors of the second differentially coupled pair; and (f) current feedback circuitry receiving a second portion of the mirrored reference current and summing the second portion with the reference current at an output of the first current mirror circuitry so as to reduce the mirrored reference current when the common mode voltage is less than the first reference voltage. ### Claim 2 (depends on 1) The amplifier circuitry of claim 1 wherein the first pair of differentially coupled input transistors includes P-channel first and second input transistors, the second pair of differentially coupled input transistors includes N-channel third and fourth input transistors, and wherein the second current mirror circuitry includes a P-channel first current mirror control transistor and a P-channel first current mirror output transistor, a W/L ratio (channel-width-to-channel-length ratio) of the first current mirror output transistor being a ratio N times a W/L ratio of the first current mirror control transistor. ### Claim 3 (depends on 2) The amplifier circuitry of claim 2 wherein a W/L ratio of the first current steering transistor is a ratio M times a W/L ratio of the second current steering transistor. ### Claim 4 (depends on 3) The amplifier circuitry of claim 3 wherein the third current mirror circuitry includes a N-channel second current mirror control transistor and a N-channel second current mirror output transistor, a W/L ratio (channel-width-to-channel-length ratio) of the second current mirror output transistor being 1+(N+1)/M times a W/L ratio of the second current mirror control transistor so as to cause the second tail current to have the same value when the common mode voltage is greater than the first reference voltage that the first tail current has when the common mode voltage is less than the first reference voltage. ### Claim 5 (depends on 3) The amplifier circuitry of claim 3 wherein the current steering circuitry includes P-channel first and second current steering transistors having sources coupled to sources of the first and second input transistors, gates of the first and second current steering transistors being coupled to receive the first reference voltage, and wherein the current feedback circuitry includes the second current steering transistor, the second current steering transistor having a gate coupled to receive the first reference voltage. ### Claim 6 (depends on 5) The amplifier circuitry of claim 5 wherein the first current mirror circuitry includes a N-channel third current mirror control transistor and a N-channel third current mirror output transistor having a drain coupled to a drain of the first current mirror control transistor. ### Claim 7 (depends on 6) The amplifier circuitry of claim 6 wherein the current feedback circuitry includes a N-channel diode-connected transistor coupled between a drain of the second current steering transistor and a summing conductor coupled to a drain of the third current mirror output transistor to cause a reduced amount of current to flow through the first current mirror control transistor when the common mode input voltage is greater than the first reference voltage. ### Claim 8 (depends on 7) The amplifier circuitry of claim 7 wherein a drain of the second current mirror control transistor is coupled to the drain of the first current steering transistor by means of a N-channel first cascode transistor having a gate coupled to receive a second reference voltage, and wherein a drain of the second current mirror output transistor is coupled to sources of the third and fourth input transistors by means of a N-channel second cascode transistor that is matched to the second current mirror output transistor. ### Claim 9 (depends on 8) The amplifier circuitry of claim 8 wherein a drain of the first current mirror output transistor is coupled to the source of the first current steering transistor by means of a third cascode transistor having a gate coupled to receive the first reference voltage. ### Claim 10 (depends on 5) The amplifier circuitry of claim 5 wherein a W/L ratio of the second current steering transistor is matched to a W/L ratio of the first current steering transistor to cause currents therein to be equal. ### Claim 11 (depends on 10) The amplifier circuitry of claim 10 wherein the ratio N is 10. ### Claim 12 (depends on 1) The amplifier circuitry of claim 1 wherein an output of the folded cascode stage is coupled to an input of a class AB output stage. ### Claim 13 (depends on 6) The amplifier circuitry of claim 6 wherein the first current mirror circuitry includes a constant current source coupled to a drain of a N-channel cascode transistor having a source coupled to a drain of the third current mirror control transistor. ### Claim 14 (depends on 2) The amplifier circuitry of claim 2 including a balancing circuit coupled to a drain of the first current mirror control transistor and a drain of the first current mirror output transistor. ### Claim 15 A method of reducing waste bias current in amplifier circuitry including i. a first pair of differentially coupled input transistors, a differential input voltage being coupled between gates of the first pair, and a second pair of differentially coupled input transistors, the differential input signal also being coupled between gates of the second pair, drains of the first and second pairs of differentially coupled input transistors being coupled to a folded-cascode stage, ii. first current mirror circuitry for generating a reference current, iii. second current mirror circuitry receiving the reference current and producing a mirrored reference current, and iv. first current steering circuitry operative to steer the mirrored reference current as a first tail current through the first pair of differentially coupled input transistors when a common mode voltage associated with the differential input voltage exceeds a first reference voltage, the method comprising: (a) amplifying a first portion of the mirrored reference current when the common mode voltage is greater than the first reference voltage to produce a second tail current for the second differentially coupled pair of transistors; and (b) feeding a second portion of the mirrored reference current back to an output of the first current mirror and summing the second portion of the mirrored reference current with the reference current so as to reduce the first portion of the mirrored reference current when the common mode voltage is greater than the first reference voltage. ### Claim 16 (depends on 1, 15) The method of claim 15 wherein the amplifier circuitry of claim 1 wherein the first pair of differentially coupled input transistors includes P-channel first and second input transistors, the second pair of differentially coupled input transistors includes N-channel third and fourth input transistors, and wherein the second current mirror circuitry includes a P-channel first current mirror control transistor and a P-channel first current mirror output transistor, the method including providing a W/L ratio (channel-width-to-channel-length ratio) of the first current mirror output transistor equal to a ratio N times a W/L ratio of the first current mirror control transistor and also providing a W/L ratio of the first current steering transistor equal to a ratio M times a W/L ratio of the second current steering transistor, wherein the third current mirror circuitry includes a N-channel second current mirror control transistor and a N-channel second current mirror output transistor, the method including providing a W/L ratio (channel-width-to-channel-length ratio) of the second current mirror output transistor equal to 1+(N+1)/M times a W/L ratio of the second current mirror control transistor so as to cause the second tail current to have the same value when the common mode voltage is greater than the first reference voltage that the first tail current has when the common mode voltage is less than the first reference voltage. ### Claim 17 Amplifier circuitry comprising: (a) a first pair of differentially coupled input transistors, a differential input voltage being coupled between gates of the first pair, and a second pair of differentially coupled input transistors, the differential input signal also being coupled between gates of the second pair, drains of the first and second pairs of differentially coupled input transistors being coupled to a folded cascode stage; (b) first current mirror circuitry for generating a reference current; (c) second current mirror circuitry receiving the reference current and producing a mirrored reference current; (d) current steering circuitry operative to steer the mirrored reference current as a first tail current through the first pair of differentially coupled input transistors when a common mode voltage associated with the differential input voltage exceeds a first reference voltage; (e) means for amplifying a first portion of the mirrored reference current when the common mode voltage is greater than the first reference voltage to produce a second tail current for the second differentially coupled pair of transistors; and (f) means for feeding a second portion of the mirrored reference current back to an output of the first current mirror and summing the second portion of the mirrored reference current with the reference current so as to reduce the second portion of the mirrored reference current when the common mode voltage is greater than the first reference voltage. ### Claim 18 (depends on 1, 17) The amplifier circuitry of claim 17 wherein the amplifier circuitry of claim 1 wherein the first pair of differentially coupled input transistors includes P-channel first and second input transistors, the second pair of differentially coupled input transistors includes N-channel third and fourth input transistors, and wherein the second current mirror circuitry includes a P-channel first current mirror control transistor and a P-channel first current mirror output transistor, a W/L ratio (channel-width-to-channel-length ratio) of the first current mirror output transistor being equal to a ratio N times a W/L ratio of the first current mirror control transistor and a W/L ratio of the first current steering transistor being equal to a ratio M times a W/L ratio of the second current steering transistor, wherein the third current mirror circuitry includes a N-channel second current mirror control transistor and a N-channel second current mirror output transistor, a W/L ratio (channel-width-to-channel-length ratio) of the second current mirror output transistor being equal to 1+(N+1)/M times a W/L ratio of the second current mirror control transistor so as to cause the second tail current to have the same value when the common mode voltage is greater than the first reference voltage that the first tail current has when the common mode voltage is less than the first reference voltage.