# US 7,411,448 B2 · Class-D amplifier

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,411,448 B2
- Document ID: US7411448B2
- Status: Granted
- Kind: B2
- Application number: 11/818,492
- Filed: 2007-06-14
- Published: 2007-10-25
- Granted: 2008-08-12
- Earliest claimed: 2004-04-30
- Assignees: Yamaha Corporation
- Inventors: Morito Morishima
- Web page: https://patentgrep.com/patent/US7411448B2

## CPC

- H03F 3/217: Class D power amplifiers; Switching amplifiers
- H03F 1/3247: {using feedback acting on predistortion circuits (H03F1/3264 takes precedence)}
- H03F 3/38: DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers {(switched capacitor amplifiers H03F3/005)}
- H03F 2200/331: Sigma delta modulation being used in an amplifying circuit
- H03F: AMPLIFIERS

## Abstract

A PWM circuit converts output data of a calculator to a pulse width modulation signal, and outputs it to a load (speaker) through a buffer amplifier and a low-pass filter. A digital low-pass filter has the same filter characteristic as a low-pass filter. An error calculator calculates the error Δ(z) between the input data and the output of the filter, and outputs it to the calculator. The output of the filter becomes a digital signal having substantially the same digitalized waveform as an analog signal applied to the load, and also no distortion contains in the digital signal. Accordingly, the output data Δ(z) of the error calculator becomes data corresponding to the distortion of the output signal. In the calculator, the data Δ(z) is subtracted from the input data, and the subtraction result is applied to the PWM circuit to reduce the distortion.

## Claims

### Claim 1

A Class-D amplifier comprising:
a delaying circuit that outputs signals respectively obtained by delaying rising or falling of a master clock by m/n period, where n is an integer of 2 or more and m is an integer smaller than n;
a selecting circuit for selecting one of output signals of the delay circuit on the basis of a first group of bits of an input signal input to an input terminal of the Class-D amplifier; and
a PWM circuit that converts a second group of the bits of the input signal to a pulse width modulation signal on the basis of the master clock, and generates a pulse signal that rises or falls at a timing indicated by the second group of the bits of the input signal and falls or rises at a timing delayed from the falling or rising timing indicated by the second group of bits by a time indicated by an output of the selecting circuit.

### Claim 2 (depends on 1)

The Class-D amplifier according to claim 1, wherein the delaying circuit comprises:
a ring oscillator comprising a plurality of delay amount variable inverters arranged in a ring shape;
a phase comparator that detects a phase difference between the master clock and an output of the ring oscillator;
a delay amount controller that controls a delay amount of each of the inverters; and
a low-pass filter that extracts low-frequency components of an output of the phase comparator and outputs the low-frequency components to an input terminal of the delay amount controller.