# US 7,411,437 B2 · Triggering events at fractions of a clock cycle > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,437 B2 - Document ID: US7411437B2 - Status: Granted - Kind: B2 - Application number: 11/292,477 - Filed: 2005-12-02 - Published: 2007-06-07 - Granted: 2008-08-12 - Earliest claimed: 2005-12-02 - Assignees: Agilent Technologies, Inc. - Inventors: Dietrich Werner Vook; Vamsi Krishna Srikantam; Andrew Fernandez - Web page: https://patentgrep.com/patent/US7411437B2 ## CPC - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - H03K 5/135: by the use of time reference signals, e.g. clock signals - H03K 2005/00058: {controlled by a digital setting} - H03K 2005/00241: {using shift registers} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or more delay circuits that trigger the event signal at a predetermined phase of the clock cycle by moving the event signal from a first clock domain to another clock domain. By triggering the event at a phase division, the triggering circuit outputs signals at a rate faster than the clock cycle. ## Claims ### Claim 1 A triggering circuit, comprising: two or more input circuits, each input circuit arranged such that each input circuit receives an input signal and one of the input circuits receives a phase selection signal and outputs an event signal in response to receiving the input signal; and two or more delay circuits, wherein each delay circuit is in electrical communication with one of the input circuits, and wherein one delay circuit receives the event signal and is configured to trigger the event signal at a predetermined phase of a clock cycle, wherein the two or more delay circuits comprise one or more delay elements, and wherein at least one delay element triggers the event signal such that the event signal moves from one clock domain to another clock domain. ### Claim 2 (depends on 1) The triggering circuit as defined in claim 1, wherein at least one delay element is one of a flip-flop or a latch. ### Claim 3 (depends on 1) The triggering circuit as defined in claim 1, wherein at least one delay element in the delay circuit receives a clock having a predetermined phase and triggers the event signal at the predetermined phase. ### Claim 4 (depends on 3) The triggering circuit as defined in claim 3, wherein one or more other delay elements arranged such that the event signal is triggered at a predetermined time. ### Claim 5 (depends on 3) The triggering circuit as defined in claim 3, wherein at least one delay element triggers the event signal at a predetermined phase such that the event signal is triggered at a fraction of a full clock cycle. ### Claim 6 (depends on 1) The triggering circuit as defined in claim 1, wherein the two or more of delay circuits forms an array of the size N by M, wherein N is a number of delay circuits and M is a number of delay elements in each delay circuit. ### Claim 7 (depends on 6) The triggering circuit as defined in claim 6, wherein the number of delay circuits N equals a number of phase divisions available for the clock cycle. ### Claim 8 (depends on 7) The triggering circuit as defined in claim 7, wherein the phase divisions are uniform. ### Claim 9 (depends on 7) The triggering circuit as defined in claim 7, wherein the phase divisions are non-uniform. ### Claim 10 A triggering circuit, comprising: two or more input circuits, each input circuit arranged such that each input circuit receives an input signal and one of the input circuits receives a phase selection signal and outputs an event signal in response to receiving the input signal; and two or more delay circuits, wherein each delay circuit is in electrical communication with one of the input circuits, and wherein one delay circuit receives the event signal and is configured to trigger the event signal at a predetermined phase of a clock cycle; wherein at least one delay circuit, comprising two or more delay elements, moves the event signal from a first clock domain in which the event signal was generated to a second clock domain in which the event signal is output. ### Claim 11 (depends on 10) The triggering circuit as defined in claim 10, wherein there is a delay between generation of a first event signal from a first delay element and the generation of a second event signal from a second delay element. ### Claim 12 (depends on 11) The triggering circuit as defined in claim 11, wherein the delay allows for at least one of set-up times, hold-times, or propagation delays. ### Claim 13 A triggering circuit, comprising: two or more input circuits, each input circuit arranged such that each input circuit receives an input signal and one of the input circuits receives a phase selection signal and outputs an event signal in response to receiving the input signal; two or more delay circuits, wherein each delay circuit is in electrical communication with one of the input circuits, and wherein one delay circuit receives the event signal and is configured to trigger the event signal at a predetermined phase of a clock cycle, thereby moving the event signal from a first clock domain having a first phase in which the event signal was generated to a second clock domain having a second phase; and an output circuit in electrical communication with each delay circuit such that the output circuit receives the event signal output from one of the delay circuits and outputs the event signal; wherein the output circuit is an OR gate. ### Claim 14 A triggering circuit, comprising: two or more input circuits, each input circuit arranged such that each input circuit receives an input signal and one of the input circuits receives a phase selection signal and outputs an event signal in response to receiving the input signal; and two or more delay circuits, wherein each delay circuit is in electrical communication with one of the input circuits, and wherein one delay circuit receives the event signal and is configured to trigger the event signal at a predetermined phase of a clock cycle, thereby moving the event signal from a first clock domain having a first phase in which the event signal was generated to a second clock domain having a second phase; wherein at least one input circuit is an AND gate. ### Claim 15 A method for triggering an event signal at a predetermined time, comprising: receiving an input signal at an input circuit; receiving a phase selection signal at the input circuit; generating an event signal, from the input circuit, in response to the phase selection signal and the input signal; receiving the event signal at a delay circuit, wherein the delay circuit comprises one or more delay elements; and triggering, by one of the delay elements, the event signal at a predetermined phase of a clock cycle, wherein the event signal moves from one clock domain to another clock domain. ### Claim 16 (depends on 15) The method for triggering as defined in claim 15, wherein triggering comprises: outputting the event signal from a delay circuit, wherein the delay circuit triggers the event signal at the predetermined phase and at a predetermined time. ### Claim 17 (depends on 16) The method for triggering as defined in claim 16, wherein outputting comprises: outputting the event signal from one or more delay elements in the delay circuit, wherein each delay element receives a clock having a predetermined phase, and wherein the event signal is output at the predetermined phase. ### Claim 18 (depends on 15) The method for triggering as defined in claim 15, wherein the input signal is received at two or more input circuits, wherein the phase selection signal is received at one input circuit, and triggering comprises outputting the event signal from the input circuit that received the phase selection signal. ### Claim 19 (depends on 15) The method for triggering as defined in claim 15, wherein triggering comprises: receiving the event signal at an output circuit in electrical communication with two or more delay circuits; and outputting the event signal from the output circuit.