# US 7,411,435 B2 · Duty detection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,435 B2 - Document ID: US7411435B2 - Status: Granted - Kind: B2 - Application number: 11/346,416 - Filed: 2006-02-03 - Published: 2006-08-03 - Granted: 2008-08-12 - Earliest claimed: 2005-02-03 - Assignees: Elpida Memory, Inc. - Inventors: Atsuko Monma; Kanji Oishi - Web page: https://patentgrep.com/patent/US7411435B2 ## CPC - H03K 5/1565: {the output pulses having a constant duty cycle} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the integration circuit; a latch circuit for latching the output of the amplifier; a control circuit for controlling the operation timings of each component; a bias circuit for feeding a BIAS signal to the integration circuit; and a frequency monitor circuit unit for monitoring the frequency of the clock signal. The frequency monitor circuit unit is a circuit component used when the power source is turned on, during resetting, and when other initial settings are performed, and detects the actual frequency of the clock signal and adjusts the amount of charging or discharging of the capacitors C1 through C4 in the integration circuit according to this actual frequency. ## Claims ### Claim 1 A duty detection circuit comprising: an integration circuit that includes first and second capacitors charged or discharged in synchrony with first and second clock signals, respectively; a duty correction signal outputting circuit that outputs a duty correction signal based on a potential difference between the first and second capacitors; and a frequency monitor circuit that adjusts an amount of charging or an amount of discharging of the first and second capacitors by changing at least a charging time or a discharging time of the first and second capacitors based on a frequency of the first and second clock signals. ### Claim 2 (depends on 1) The duty detection circuit as claimed in claim 1, wherein the frequency monitor circuit increases the amount of charging or amount of discharging of the first and second capacitors in response to the frequency of the first and second clock signals being higher than a reference frequency. ### Claim 3 (depends on 2) The duty detection circuit as claimed in claim 2, wherein the frequency monitor circuit decreases the amount of charging or amount of discharging of the first and second capacitors in response to the frequency of the first and second clock signals being lower than the reference frequency. ### Claim 4 (depends on 3) The duty detection circuit as claimed in claim 3, wherein the frequency monitor circuit adjusts the amount of charging or amount of discharging of the first and second capacitors by further changing a charging rate or discharging rate of the first and second capacitors. ### Claim 5 (depends on 4) The duty detection circuit as claimed in claim 4, wherein the integration circuit comprising: a first integration transistor for charging or discharging the first capacitor during a time period in which the first clock signal is high-level; a second integration transistor for charging or discharging the second capacitor during a time period in which the second clock signal is high-level; and a bias transistor for defining a bias current quantity flowing to the first and second integration transistors, and the frequency monitor circuit changing the charging rate or discharging rate of the first and second capacitors by changing the bias current quantity defined by the bias transistor. ### Claim 6 (depends on 3) The duty detection circuit as claimed in claim 3, wherein the integration circuit comprising: a first integration transistor for charging or discharging the first capacitor during a time period in which the first clock signal is high-level; a second integration transistor for charging or discharging the second capacitor during a time period in which the second clock signal is high-level; an activation transistor for defining an integration operation time period that is a time period during which a current flows to the first or second integration transistor as an integer multiple of a period of the first and second clock signals, and the frequency monitor circuit changing the charging time or discharging time of the first and second capacitors by changing the integration operation time period defined by the activation transistor. ### Claim 7 (depends on 1) The duty detection circuit as claimed in claim 1, wherein the frequency monitor circuit decreases the amount of charging or amount of discharging of the first and second capacitors in response to the frequency of the first and second clock signals being lower than a reference frequency. ### Claim 8 (depends on 1) The duty detection circuit as claimed in claim 1, wherein the frequency monitor circuit adjusts the amount of charging or amount of discharging of the first and second capacitors by further changing a charging rate or discharging rate of the first and second capacitors. ### Claim 9 (depends on 8) The duty detection circuit as claimed in claim 8, wherein the integration circuit comprising: a first integration transistor for charging or discharging the first capacitor during a time period in which the first clock signal is high-level; a second integration transistor for charging or discharging the second capacitor during a time period in which the second clock signal is high-level; and a bias transistor for defining a bias current quantity flowing to the first and second integration transistors, and the frequency monitor circuit changing the charging rate or discharging rate of the first and second capacitors by changing the bias current quantity defined by the bias transistor. ### Claim 10 (depends on 1) The duty detection circuit as claimed in claim 1, wherein the integration circuit comprising: a first integration transistor for charging or discharging the first capacitor during a time period in which the first clock signal is high-level; a second integration transistor for charging or discharging the second capacitor during a tine period in which the second clock signal is high-level; an activation transistor for defining a integration operation time period that is a time period during which a current flows to the first or second integration transistor as an integer multiple of a period of the first and second clock signals, and the frequency monitor circuit changing the charging time or discharging time of the first and second capacitors by changing the integration operation time period defined by the activation transistor. ### Claim 11 A duty detection circuit comprising: an integration circuit that includes first and second capacitors charged or discharged in synchrony with first and second clock signals, respectively; a duty correction signal outputting circuit that outputs a duty correction signal based on a potential difference between the first and second capacitors; and a frequency monitor circuit that adjusts an amount of charging or an amount of discharging of the first and second capacitors according to a frequency of the first and second clock signals, wherein the frequency monitor circuit comprises a replica integration circuit including a third capacitor, for charging or discharging the third capacitor in synchrony with one of the first and second clock signals; and detects the frequency of the first and second clock signals based at least on a size relationship between a potential of the third capacitor and a reference potential. ### Claim 12 (depends on 11) The duty detection circuit as claimed in claim 11, wherein a charging rate or discharging rate of the third capacitor differs from a charging rate or discharging rate of the first and second capacitors. ### Claim 13 (depends on 11) The duty detection circuit as claimed in claim 11, wherein the frequency monitor circuit increases the amount of charging or amount of discharging of the first and second capacitors in response to the frequency of the first and second clock signals being higher than a reference frequency. ### Claim 14 (depends on 11) The duty detection circuit as claimed in claim 11, wherein the frequency monitor circuit decreases the amount of charging or amount of discharging of the first and second capacitors in response to the frequency of the first and second clock signals being lower than a reference frequency. ### Claim 15 (depends on 11) The duty detection circuit as claimed in claim 11, wherein the frequency monitor circuit adjusts the amount of charging or amount of discharging of the first and second capacitors by changing at least a charging rate or discharging rate of the first and second capacitors. ### Claim 16 (depends on 15) The duty detection circuit as claimed in claim 15, wherein the integration circuit comprising: a first integration transistor for charging or discharging the first capacitor during a time period in which the first clock signal is high-level; a second integration transistor for charging or discharging the second capacitor during a time period in which the second clock signal is high-level; and a bias transistor for defining a bias current quantity flowing to the first and second integration transistors, and the frequency monitor circuit changing the charging rate or discharging rate of the first and second capacitors by changing the bias current quantity defined by the bias transistor. ### Claim 17 (depends on 11) The duty detection circuit as claimed in claim 11, wherein the frequency monitor circuit adjusts the amount of charging or amount of discharging of the first and second capacitors by changing at least a charging time or discharging time of the first and second capacitors. ### Claim 18 (depends on 17) The duty detection circuit as claimed in claim 17, wherein the integration circuit comprising: a first integration transistor for charging or discharging the first capacitor during a time period in which the first clock signal is high-level; a second integration transistor for charging or discharging the second capacitor during a time period in which the second clock signal is high-level; an activation transistor for defining an integration operation time period that is a time period during which a current flows to the first or second integration transistor as an integral multiple of a period of the first and second clock signals; and the frequency monitor circuit changing the charging time or discharging time of the first and second capacitors by changing the integration operation time period defined by the activation transistor. ### Claim 19 A duty detection circuit comprising: an integration circuit that includes first and second capacitors charged or discharged in synchrony with first and second clock signals, respectively; a duty correction signal outputting circuit that outputs a duty correction signal based on a potential difference between the first and second capacitors; and a frequency monitor circuit that adjusts an amount of charging or an amount of discharging of the first and second capacitors according to a frequency of the first and second clock signals, wherein the frequency monitor circuit comprises a first replica integration circuit including a third capacitor, for charging or discharging the third capacitor in synchrony with one of the first and second clock signals; and a second replica integration circuit including a fourth capacitor, for charging or discharging the fourth capacitor at a rate that differs from a charging rate or discharging rate of the third capacitor in synchrony with one of the first and second clock signals; and detects the frequency of the first and second clock signals based at least on a level relationship between potentials of the third and fourth capacitors and a reference potential. ### Claim 20 (depends on 19) The duty detection circuit as claimed in claim 19, wherein a charging rate or discharging rate of the third capacitor is essentially the same as a charging rate or discharging rate of the first and second capacitors. ### Claim 21 (depends on 19) The duty detection circuit as claimed in claim 19, wherein the frequency monitor circuit increases the amount of charging or amount of discharging of the first and second capacitors in response to the frequency of the first and second clock signals being higher than a reference frequency. ### Claim 22 (depends on 19) The duty detection circuit as claimed in claim 19, wherein the frequency monitor circuit decreases the amount of charging or amount of discharging of the first and second capacitors in response to the frequency of the first and second clock signals being lower than a reference frequency. ### Claim 23 (depends on 19) The duty detection circuit as claimed in claim 19, wherein the frequency monitor circuit adjusts the amount of charging or amount of discharging of the first and second capacitors by changing at least a charging rate or discharging rate of the first and second capacitors. ### Claim 24 (depends on 23) The duty detection circuit as claimed in claim 23, wherein the integration circuit comprising: a first integration transistor for charging or discharging the first capacitor during a time period in which the first clock signal is high-level; a second integration transistor for charging or discharging the second capacitor during a time period in which the second clock signal is high-level; and a bias transistor for defining a bias current quantity flowing to the first and second integration transistors, and the frequency monitor circuit changing the charging rate or discharging rate of the first and second capacitors by changing the bias current quantity defined by the bias transistor. ### Claim 25 (depends on 19) The duty detection circuit as claimed in claim 19, wherein the frequency monitor circuit adjusts the amount of charging or amount of discharging of the first and second capacitors by changing at least a charging time or discharging time of the first and second capacitors. ### Claim 26 (depends on 25) The duty detection circuit as claimed in claim 25, wherein the integration circuit comprising: a first integration transistor for charging or discharging the first capacitor during a time period in which the first clock signal is high-level; a second integration transistor for charging or discharging the second capacitor during a time period in which the second clock signal is high-level; an activation transistor for defining an integration operation time period that is a time period during which a current flows to the first or second integration transistor as an integer multiple of a period of the first and second clock signals, and the frequency monitor circuit changing the charging time or discharging time of the first and second capacitors by changing the integration operation time period defined by the activation transistor. ### Claim 27 A duty detection circuit comprising: a main integration circuit that charges or discharges a first capacitor in synchrony with a first clock signal and charges or discharges a second capacitor in synchrony with a second clock signal; a first replica integration circuit that charges or discharges a third capacitor in synchrony with one of the first and second clock signals; a first amplifier that detects a potential difference between the first and second capacitors; a second amplifier that detects a potential difference between the third capacitor and a reference voltage; and a determination circuit that adjusts an amount of charging or discharging of the first and second capacitors based at least on an output of the second amplifier. ### Claim 28 (depends on 27) The duty detection circuit as claimed in claim 27, wherein the main integration circuit and the first replica integration circuit have substantially the same circuit configuration. ### Claim 29 (depends on 27) The duty detection circuit as claimed in claim 27, further comprising: a second replica integration circuit that charges or discharges a fourth capacitor in synchrony with one of the first and second clock signals in a different charging or discharging rate from the first replica integration circuit; and a third amplifier that detects a potential difference between the fourth capacitor and the reference voltage, wherein the determination circuit adjusts the amount of charging or discharging of the first and second capacitors based on outputs of the second and third amplifiers. ### Claim 30 (depends on 27) The duty detection circuit as claimed in claim 27, wherein the determination circuit changes the charging rate or discharging rate of the first and second capacitors. ### Claim 31 (depends on 27) The duty detection circuit as claimed in claim 27, wherein the determination circuit changes the charging time or discharging time of the first and second capacitors. ### Claim 32 (depends on 27) The duty detection circuit as claimed in claim 27, wherein the determination circuit increases the charging rate or discharging rate of the first and second capacitors when the frequency of the first and second clock signals is higher than a first reference frequency, and shortens the charging time or discharging time of the first and second capacitors when the frequency of the first and second clock signals is lower than a second reference frequency.