# US 7,411,434 B2 · Digitally programmable delay circuit with process point tracking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,434 B2 - Document ID: US7411434B2 - Status: Granted - Kind: B2 - Application number: 11/684,087 - Filed: 2007-03-09 - Published: 2007-06-28 - Granted: 2008-08-12 - Earliest claimed: 2005-01-28 - Assignees: Altera Corporation - Inventors: Adam L. Carley; Daniel J. Allen; James E. Mandry - Web page: https://patentgrep.com/patent/US7411434B2 ## CPC - H03K 5/133: using a chain of active delay devices - H03K 2005/00065: {by current control, e.g. by parallel current control transistors} - H03K 2005/00221: {where the conduction path of the different output FET's is connected in parallel with different gate control, e.g. having different sizes or thresholds, or coupled through different resistors} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other and in a ladder configuration. The overall delay imposed on the edge after it has passed through both sub-circuits has delay contributions from both types of transistors. The delay circuit may have enhanced performance because of finer delay control granularity by providing a first circuit stage that comprises a plurality of transistors for relatively fine delay adjustment to the edge and a second circuit stage that comprises a plurality of transistors for relatively coarse delay adjustment to the edge. A combination of one or more of the transistors in the first and second circuit stages may be selected to produce numerous steps or increments of delay adjustability. ## Claims ### Claim 1 A clock system comprising: a. a ring oscillator circuit that generates a plurality of uniquely phased oscillator transition signals from which a clock signal is generated; b. a comparator circuit coupled to the ring oscillator circuit that compares a speed of the ring oscillator circuit with a reference signal to generate a tracking value that is a measure of the instantaneous process, voltage and temperature conditions of the integrated circuit; and c. a computation circuit coupled to the comparator circuit that generates a delay control signal based on the tracking value and a desired delay amount; and d. a digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to an output of the ring oscillator circuit carrying the clock signal having an edge to be delayed, wherein one or more of the transistors are selected by the delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on the desired delay amount and said tracking value. ### Claim 2 (depends on 1) The clock system of claim 1, wherein the digitally programmable delay circuit further comprises a selector circuit that is coupled to receive as input the delay control signal, wherein the delay control signal comprises a digital selection code, wherein in response to the delay selection code the selector circuit selects and activates one or more of the plurality of transistors in the digitally programmable delay circuit. ### Claim 3 A clock system implemented in an integrated comprising: a. a ring oscillator circuit that generates a plurality of uniquely phased oscillator transition signals from which a clock signal is generated; b. a comparator circuit coupled to the ring oscillator circuit that compares a speed of the ring oscillator circuit with a reference signal to generate a tracking value that is a measure of the instantaneous process, voltage and temperature conditions of the integrated circuit; and c. a plurality of processing channels each comprising: i. a computation circuit coupled to the comparator circuit that generates a delay control signal based on the tracking value and a desired delay amount; and ii. a digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and coupled to an output of the ring oscillator circuit carrying the clock signal having an edge to be delayed, wherein one or more of the transistors are selected by the delay control signal delay the edge, wherein the delay control signal is based on the desired delay amount and said tracking value; and iii. an edge generation circuit connected to the digitally programmable delay circuit and which generates a signal edge based on an output of the digitally programmable delay circuit. ### Claim 4 (depends on 3) The clock system of claim 3, wherein the computation circuit in each processing channel generates a different delay control signal depending on a corresponding desired delay amount for that processing channel and said tracking value. ### Claim 5 (depends on 3) The clock system of claim 3, wherein each processing channel further comprises a combiner logic circuit connected to an output of the edge generation circuit that combines signal edges output by the edge detection circuit in the corresponding processing channel to generate an output clock signal for that processing channel. ### Claim 6 (depends on 5) The clock system of claim 5, wherein the combiner logic circuit in at least one of the processing channels is further connected to an output of the edge detection circuit of at least one other processing channel. ### Claim 7 (depends on 3) The clock system of claim 3, wherein the digitally programmable delay circuit further comprises a selector circuit that is coupled to receive as input the delay control signal for the corresponding processing channel, wherein the delay control signal comprises a digital selection code, wherein in response to the delay selection code the selector circuit selects and activates one or more of the plurality of transistors in the digitally programmable delay circuit. ### Claim 8 (depends on 3) The clock system of claim 3, wherein the plurality of transistors in the digitally programmable delay circuit comprises a plurality of transistors of a first type connected in parallel with each other and a plurality of transistors of a second type connected in parallel with each other, and wherein some of the plurality of transistors of the first type impose a different delay amount on the edge when activated and some of the plurality of transistors of the second type impose a different delay amount on the edge when activated. ### Claim 9 (depends on 3) The clock system of claim 3, wherein the plurality of transistors in the digitally programmable delay circuit comprises a first sub-circuit and a second sub-circuit, the first sub-circuit comprising a plurality of P-type transistors connected in parallel with each other, some of the P-type transistors having different effective widths, and the second sub-circuit comprising a corresponding plurality of N-type transistors connected in parallel with each other, some of the N-type transistors having different effective widths, wherein the first sub-circuit and the second sub-circuit are connected in series with each other so that one of the first and second sub-circuits delays the edge followed by the other of the first and second sub-circuits further delaying the edge. ### Claim 10 (depends on 9) The clock system of claim 9, wherein a P-type transistor in the first sub-circuit and a corresponding N-type transistor in the second sub-circuit are selected together in response to the delay control signal. ### Claim 11 (depends on 9) The clock system of claim 9, wherein each of the plurality of P-type transistors in the first sub-circuit have different effective widths so as to span in increments a delay range, and each of the N-type transistors in the second sub-circuit have different effective widths so as to span in increments a delay range. ### Claim 12 (depends on 9) The clock system of claim 9, and further comprising an N-type transistor connected in parallel with the plurality of P-type transistors in the first sub-circuit, the N-type transistor discharging voltage across the plurality of P-type transistors in the first sub-circuit during a low portion of the signal, and a P-type transistor connected in parallel with the plurality of N-type transistors in the second sub-circuit, the P-type transistor discharging voltage across the plurality of N-type transistors in the second sub-circuit during a high portion of the signal. ### Claim 13 (depends on 3) The clock system of claim 3, wherein each digitally programmable delay circuit comprises a capacitive load connected between the plurality of transistors and ground, wherein the capacitive load comprises an active capacitor having a gate, source and drain, and wherein a ratio of a gate capacitance to wire capacitance is set for matching tracking between the programmable delay circuit and the ring oscillator circuit.