US 7,411,426 B2Granted

Phase detector for RZ

AssigneeExar Corporation

InventorNam Duc Nguyen

Life of this patent

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Abstract

A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in response to unassertion of the first signal. The phase detector may include combinatorial logic gates, thereby to generate the third and fourth signals in response to logic levels of the first and second signals. The phase detector may include sequential logic gates, thereby to generate the third and fourth signals in response to transitions of the first and second signals.

Claims2

Dependent claims

A phase detector comprising;

a first pulse generator responsive to a data signal;
a first flip-flop having a clock terminal responsive to an output of the first pulse generator;
said first flip-flop having a data terminal coupled to a first voltage;
a second pulse generator responsive to a clock signal;
and
a second flip-flop having a clock terminal responsive to an output of the second pulse generator;
said second flip-flop having a data terminal coupled to the first voltage;
a third pulse generator responsive to said data signal, wherein a reset terminal of the first flip-flop is responsive to an output of the second pulse generator, wherein the reset terminal of each of the first and second flip-flops is further responsive to an output of the second pulse generator, wherein the reset terminal of each of the first and second flip-flops is further responsive to a reset signal, wherein each of said first, second and third pulse generators comprises a first logic block performing an inverse operation, a second logic block performing a delay operation, and a third logic block performing a NOR operation.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/429,462Filed 5 May 2006 · continuation in part
Priority: 20 Jul 2004
Published: US 2007/0035333 A115 Feb 2007
Granted: 12 Aug 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03D 13/002
In which a pulse counter is used followed by a conversion into an analog signal: the counter being an up-down counter
H03D 13/004
In which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means: the logic means…
H03D 13/00
Circuits for comparing the phase or frequency of two mutually-independent oscillations
H03L 7/091
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: the phase or…