# US 7,411,425 B2 · Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,425 B2 - Document ID: US7411425B2 - Status: Granted - Kind: B2 - Application number: 11/168,691 - Filed: 2005-06-28 - Published: 2006-12-28 - Granted: 2008-08-12 - Earliest claimed: 2005-06-28 - Assignees: International Business Machines Corporation - Inventors: Wendy Ann Belluomini; Aniket Mukul Saha - Web page: https://patentgrep.com/patent/US7411425B2 ## CPC - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers. ## Claims ### Claim 1 A method of operating a dynamic logical circuit, comprising: responsive to a clock signal pre-charge phase, pre-charging a summing node of said dynamic logical circuit to a predetermined first power supply rail voltage by supplying a current through a pre-charge circuit, wherein said clock signal has a voltage substantially equal to a predetermined second power supply rail voltage opposite said first power supply rail voltage during said clock signal pre-charge phase; responsive to a clock signal evaluation phase and further to a plurality of logical signal inputs assuming a predetermined combination of logical values, discharging said summing node to said second power supply rail voltage, wherein said clock signal has an evaluate phase voltage substantially differing from said first power supply rail voltage during said clock signal evaluation phase in a direction of said second power supply rail; and providing a logical output corresponding to a value of said summing node. ### Claim 2 (depends on 1) The method of claim 1, wherein the dynamic logical circuit is a limited-switch dynamic logic circuit, wherein all clocked devices within the dynamic logical circuit are clocked by said pre-charging and discharging such that all clock swings extend only between said evaluate phase voltage and said second power supply rail voltage. ### Claim 3 (depends on 1) The method of claim 1, wherein said evaluate phase voltage differs from said first power supply rail voltage by twenty to forty-five percent of the difference between said first and second power supply rail voltages. ### Claim 4 (depends on 1) The method of claim 1, wherein said evaluate phase voltage differs from said first power supply rail voltage by twenty-two to thirty-three percent of the difference between said first and second power supply rail voltages. ### Claim 5 (depends on 1) The method of claim 1, further comprising: generating said clock signal at a local clock buffer having a clock input for receiving a global clock having a voltage swing extending substantially between said first power supply rail and said second power supply rail; and distributing said clock signal to said dynamic logical circuit from a clock output of said local clock buffer. ### Claim 6 (depends on 5) The method of claim 5, wherein said local clock buffer has two power supply rail inputs, a first power supply input connected to said first power supply rail voltage and a second power supply input connected to a power supply rail having a voltage substantially equal to said evaluate phase voltage of said clock signal, and wherein said generating switches said second power supply input onto said clock output during said evaluate phase. ### Claim 7 (depends on 1) The method of claim 1, wherein said discharging is performed through a logic tree comprising at least one branch connected to said summing node, each of said at least one branch comprising at least one series connected transistor, and wherein an end of said at least one branch opposite said summing node is isolated during said pre-charging by an input foot device, and further comprising enabling said foot device during said evaluation phase of said clock with said evaluate phase voltage. ### Claim 8 (depends on 1) The method of claim 1, wherein said providing is performed by a static logic stage having a first inverter with an input connected to said summing node, and a second inverter having an input connected to an output of said first inverter and wherein said first inverter has a inverter foot device for isolating said first inverter from said second power supply rail during said pre-charge phase of said clock, and wherein said inverter foot device is enabled during said evaluation phase of said clock with said evaluate phase voltage. ### Claim 9 (depends on 1) The method of claim 1, wherein said providing is performed by a static logic stage having a first inverter with an input connected to said summing node, and a second inverter having an input connected to an output of said first inverter, wherein said input of said second inverter has a keeper, wherein said keeper has a disable device having an input connected to said clock signal for disabling said keeper during said evaluate phase of said clock, and wherein said disable device is disabled during said evaluation phase of said clock with said evaluate phase voltage.