# US 7,411,417 B1 · Selective loading of configuration data into configuration memory cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,417 B1 - Document ID: US7411417B1 - Status: Granted - Kind: B1 - Application number: 11/442,186 - Filed: 2006-05-26 - Granted: 2008-08-12 - Earliest claimed: 2006-05-26 - Assignees: Lattice Semiconductor Corporation - Inventors: David L. Rutledge; Wei Han; Yoshita Yerramilli - Web page: https://patentgrep.com/patent/US7411417B1 ## CPC - H03K 19/1776: for memories - H03K 19/17764: for reliability - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Systems and methods are disclosed herein to provide improved techniques for loading of configuration memory cells in integrated circuits, such as programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells. ## Claims ### Claim 1 A programmable logic device comprising: a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells, wherein the first bit is adapted to be programmed in response to a loading of the configuration data into the non-volatile memory. ### Claim 2 (depends on 1) The programmable logic device of claim 1, wherein the second bit is adapted to be programmed to prevent a loading of the configuration data from the non-volatile memory into the configuration memory cells. ### Claim 3 (depends on 1) The programmable logic device of claim 1, wherein the first bit is adjacent to the second bit in the non-volatile memory. ### Claim 4 (depends on 1) The programmable logic device of claim 1, further comprising a data port adapted to receive instructions to program the first and second bits. ### Claim 5 (depends on 1) The programmable logic device of claim 1, wherein the control logic comprises a register adapted to receive the first bit and the second bit from the non-volatile memory. ### Claim 6 (depends on 1) The programmable logic device of claim 1, further comprising a plurality of sense amplifiers adapted to provide the first bit and the second bit to the control logic. ### Claim 7 (depends on 1) The programmable logic device of claim 1, wherein the configuration memory cells are volatile SRAM memory cells. ### Claim 8 (depends on 1) The programmable logic device of claim 1, wherein the non-volatile memory is a flash memory. ### Claim 9 A method of controlling a programmable logic device, the method comprising: pre-programming a first bit and a second bit of a non-volatile memory with a first logic state, wherein the non-volatile memory is adapted to store the first bit, the second bit, and a plurality of configuration data; erasing the non-volatile memory, wherein the first bit and the second bit each exhibit a second logic state following the erasing; loading the configuration data into the non-volatile memory; programming the first bit with the first logic state to identify that the loading is completed; and selectively programming a second bit with the first logic state to identify whether a user desires that the configuration data be loaded into a plurality of configuration memory cells. ### Claim 10 (depends on 9) The method of claim 9, further comprising: performing a logic operation on the first bit and the second bit to obtain a logic result; and selectively loading the configuration data from the non-volatile memory into a plurality of configuration memory cells in response to the logic result. ### Claim 11 (depends on 9) The method of claim 9, wherein the method is performed in response to instructions received by the programmable logic device. ### Claim 12 (depends on 9) The method of claim 9, wherein the configuration memory cells are volatile SRAM memory cells. ### Claim 13 (depends on 9) The method of claim 9, wherein the non-volatile memory is a flash memory. ### Claim 14 (depends on 9) The method of claim 9, further comprising: reading the first bit and the second bit; and selectively loading the configuration data from the non-volatile memory into the plurality of configuration memory cells based on logic states of the first and second bits. ### Claim 15 (depends on 14) The method of claim 14, wherein the selectively loading comprises performing a logic operation on the first bit and the second bit to obtain a logic result. ### Claim 16 (depends on 14) The method of claim 14, wherein the reading and selectively loading are performed by control logic of the programmable logic device. ### Claim 17 (depends on 14) The method of claim 14, wherein the reading and selectively loading are performed in response to a powering up of the programmable logic device. ### Claim 18 (depends on 14) The method of claim 14, wherein the reading comprises loading the first bit and the second bit into a register. ### Claim 19 (depends on 14) The method of claim 14, wherein the configuration memory cells are volatile memory cells. ### Claim 20 (depends on 14) The method of claim 14, wherein the first bit is a validation bit and the second bit is a stop bit. ### Claim 21 (depends on 14) The method of claim 14, wherein the configuration data is loaded from the non-volatile memory into the plurality of configuration memory cells based on the first and second bits having opposite logic states. ### Claim 22 (depends on 21) The method of claim 21, wherein the first bit has a logical high state and the second bit has a logical low state. ### Claim 23 A programmable logic device comprising: a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data; a plurality of configuration memory cells; and control logic adapted to determine based on values of the first and second bits whether to load the configuration data from the non-volatile memory into the configuration memory cells, wherein the second bit is adapted to be programmed to prevent a loading of the configuration data from the non-volatile memory into the configuration memory cells.